7fa0819ecf
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
52 lines
1.6 KiB
C
52 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SUPERIO_INTEL_I3100_I3100_H
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#define SUPERIO_INTEL_I3100_I3100_H
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/*
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* Datasheet:
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* - Name: Intel 3100 Chipset
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* - URL: http://www.intel.com/design/intarch/datashts/313458.htm
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* - PDF: http://download.intel.com/design/intarch/datashts/31345803.pdf
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* - Revision / Date: 007, October 2008
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* - Order number: 313458-007US
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*/
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/*
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* The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is
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* very similar to a Super I/O, both in functionality and config mechanism.
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*
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* The SIW contains:
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* - UART(s)
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* - Serial interrupt controller
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* - Watchdog timer (WDT)
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* - LPC interface
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*/
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/* Logical device numbers (LDNs). */
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#define I3100_SP1 0x04 /* Com1 */
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#define I3100_SP2 0x05 /* Com2 */
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#define I3100_WDT 0x06 /* Watchdog timer */
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#define I3100_SUPERIO_CONFIG_PORT 0x4e
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#endif
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