8078e900d1
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifc85ed8b5660eca11be50fddda0cf32aa1dd611c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
133 lines
3.5 KiB
C
133 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <commonlib/helpers.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <soc/infracfg.h>
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#include <soc/pll.h>
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#include <soc/pll_common.h>
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#include <soc/pmif.h>
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#include <soc/pmif_clk_common.h>
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#include <soc/pmif_sw.h>
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#include <soc/pmif_spmi.h>
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#include <soc/spm.h>
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/* APMIXED, ULPOSC1_CON0 */
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DEFINE_BITFIELD(OSC1_CALI, 6, 0)
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DEFINE_BITFIELD(OSC1_IBAND, 13, 7)
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DEFINE_BITFIELD(OSC1_FBAND, 17, 14)
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DEFINE_BITFIELD(OSC1_DIV, 23, 18)
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DEFINE_BIT(OSC1_CP_EN, 24)
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/* APMIXED, ULPOSC1_CON1 */
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DEFINE_BITFIELD(OSC1_32KCALI, 7, 0)
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DEFINE_BITFIELD(OSC1_RSV1, 15, 8)
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DEFINE_BITFIELD(OSC1_RSV2, 23, 16)
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DEFINE_BITFIELD(OSC1_MOD, 25, 24)
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DEFINE_BIT(OSC1_DIV2_EN, 26)
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/* APMIXED, ULPOSC1_CON2 */
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DEFINE_BITFIELD(OSC1_BIAS, 7, 0)
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/* SPM, POWERON_CONFIG_EN */
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DEFINE_BIT(BCLK_CG_EN, 0)
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DEFINE_BITFIELD(PROJECT_CODE, 31, 16)
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/* SPM, ULPOSC_CON */
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DEFINE_BIT(ULPOSC_EN, 0)
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DEFINE_BIT(ULPOSC_CG_EN, 2)
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/* INFRA, MODULE_SW_CG */
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DEFINE_BIT(PMIC_CG_TMR, 0)
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DEFINE_BIT(PMIC_CG_AP, 1)
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DEFINE_BIT(PMIC_CG_MD, 2)
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DEFINE_BIT(PMIC_CG_CONN, 3)
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/* INFRA, INFRA_GLOBALCON_RST2 */
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DEFINE_BIT(PMIC_WRAP_SWRST, 0)
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DEFINE_BIT(PMICSPMI_SWRST, 14)
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/* INFRA, PMICW_CLOCK_CTRL */
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DEFINE_BITFIELD(PMIC_SYSCK_26M_SEL, 3, 0)
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/* TOPCKGEN, CLK_CFG_8 */
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DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SET, 10, 8)
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DEFINE_BIT(CLK_PWRAP_ULPOSC_INV, 12)
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DEFINE_BIT(PDN_PWRAP_ULPOSC, 15)
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/* TOPCKGEN, CLK_CFG_UPDATE1 */
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DEFINE_BIT(CLK_CFG_UPDATE1, 2)
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static void pmif_ulposc_config(void)
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{
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/* ULPOSC1_CON0 */
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SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CP_EN, 0, OSC1_DIV, 0xe,
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OSC1_FBAND, 0x2, OSC1_IBAND, 0x52, OSC1_CALI, 0x40);
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/* ULPOSC1_CON1 */
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SET32_BITFIELDS(&mtk_apmixed->ulposc1_con1, OSC1_DIV2_EN, 0, OSC1_MOD, 0,
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OSC1_RSV2, 0, OSC1_RSV1, 0x29, OSC1_32KCALI, 0);
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/* ULPOSC1_CON2 */
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SET32_BITFIELDS(&mtk_apmixed->ulposc1_con2, OSC1_BIAS, 0x40);
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}
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u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
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{
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u32 result = 0;
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/* set calibration value */
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SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CALI, cali_val);
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udelay(50);
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result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK);
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return result / 1000;
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}
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static int pmif_init_ulposc(void)
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{
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/* calibrate ULPOSC1 */
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pmif_ulposc_config();
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/* enable spm swinf */
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if (!READ32_BITFIELD(&mtk_spm->poweron_config_set, BCLK_CG_EN))
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SET32_BITFIELDS(&mtk_spm->poweron_config_set, BCLK_CG_EN, 1,
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PROJECT_CODE, 0xb16);
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/* turn on ulposc */
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SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1);
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udelay(100);
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SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_CG_EN, 1);
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return pmif_ulposc_cali(FREQ_260MHZ);
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}
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int pmif_clk_init(void)
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{
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if (pmif_init_ulposc())
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return E_NODEV;
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/* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
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SET32_BITFIELDS(&mt8192_infracfg->module_sw_cg_0_set, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
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PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
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SET32_BITFIELDS(&mtk_topckgen->clk_cfg_8, PDN_PWRAP_ULPOSC, 0, CLK_PWRAP_ULPOSC_INV,
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0, CLK_PWRAP_ULPOSC_SET, 0);
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SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update1, CLK_CFG_UPDATE1, 1);
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/* use ULPOSC1 clock */
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SET32_BITFIELDS(&mt8192_infracfg->pmicw_clock_ctrl_clr, PMIC_SYSCK_26M_SEL, 0xf);
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/* toggle SPI/SPMI sw reset */
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SET32_BITFIELDS(&mt8192_infracfg->infra_globalcon_rst2_set, PMICSPMI_SWRST, 1,
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PMIC_WRAP_SWRST, 1);
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SET32_BITFIELDS(&mt8192_infracfg->infra_globalcon_rst2_clr, PMICSPMI_SWRST, 1,
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PMIC_WRAP_SWRST, 1);
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/* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
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SET32_BITFIELDS(&mt8192_infracfg->module_sw_cg_0_clr, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
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PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
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return 0;
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}
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