4e0ec59255
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <soc/gpio.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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void bootblock_mainboard_early_init(void)
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{
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uint32_t reg;
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uint32_t *pad_config_reg;
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/* Enable the UART hardware for COM1. */
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reg = 1;
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pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
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/*
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* Set up the pads to select the UART function
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* AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Set Mode 2 for UART0_RXD
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* AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD
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*/
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pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD);
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write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,
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M2));
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pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD);
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write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,
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M2));
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}
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