8245bd25a3
Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the pre-RAM FMAP cache code, there's no point in allowing the region to be optional anymore. This patch makes the section required by the linker. If a board doesn't want to provide it, it has to select NO_FMAP_CACHE. Adding FMAP_CACHE regions to a couple more targets that I think can use them but I don't know anything about... please yell if one of these is a bad idea and I should mark them NO_FMAP_CACHE instead. Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
35 lines
933 B
Plaintext
35 lines
933 B
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Asami Doi <d0iasm.pub@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <memlayout.h>
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#include <arch/header.ld>
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/*
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* Memory map for QEMU virt machine since
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* a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (June 2019):
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*
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* 0..128MiB (0x0000_0000..0x0080_0000) is the space for a flash device.
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* 128MiB..256MiB (0x0080_0000..0x0100_0000) is used for miscellaneous device I/O.
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* 256MiB..1GiB (0x0100_0000..0x4000_0000) is reserved for possible future PCI support.
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* 1GiB.. (0x4000_0000) is RAM and the size depends on initial RAM and device memory settings.
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*/
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SECTIONS
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{
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REGION(flash, 0x00000000, CONFIG_ROM_SIZE, 8)
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DRAM_START(0x40000000)
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BOOTBLOCK(0x60010000, 64K)
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STACK(0x60020000, 62K)
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FMAP_CACHE(0x6002F800, 2K)
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ROMSTAGE(0x60030000, 128K)
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RAMSTAGE(0x60070000, 16M)
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TTB(0x61100000, 16K)
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POSTRAM_CBFS_CACHE(0x61110000, 1M)
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}
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