83f81cad7a
All boards now use per-device ACPI. This patch finishes migration by removing transitional kludges. Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7372 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
165 lines
3.3 KiB
Plaintext
165 lines
3.3 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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## Copyright (C) 2007-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc.
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##
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config NORTHBRIDGE_AMD_AMDFAM10
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bool
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select HAVE_DEBUG_RAM_SETUP
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select HAVE_DEBUG_SMBUS
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select HAVE_DEBUG_CAR
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select HYPERTRANSPORT_PLUGIN_SUPPORT
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select MMCONF_SUPPORT
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if NORTHBRIDGE_AMD_AMDFAM10
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config AGP_APERTURE_SIZE
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hex
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default 0x4000000
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config MMCONF_BUS_NUMBER
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int
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default 256
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# TODO: Reservation for heap seems excessive
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config HEAP_SIZE
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hex
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default 0xc0000
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config RAMTOP
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hex
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default 0x400000
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/amd/amdfam10/bootblock.c"
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config SB_HT_CHAIN_UNITID_OFFSET_ONLY
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bool
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default n
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config DIMM_FBDIMM
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bool
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default n
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config DIMM_DDR2
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bool
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default n
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config DIMM_DDR3
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bool
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default n
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config DIMM_REGISTERED
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bool
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default n
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if DIMM_FBDIMM
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config DIMM_SUPPORT
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hex
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default 0x0110
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endif
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if DIMM_DDR2
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if DIMM_REGISTERED
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config DIMM_SUPPORT
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hex
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default 0x0104
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endif
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if !DIMM_REGISTERED
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config DIMM_SUPPORT
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hex
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default 0x0004
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endif
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endif
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if DIMM_DDR3
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if DIMM_REGISTERED
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config DIMM_SUPPORT
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hex
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default 0x0005
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endif
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endif
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config SVI_HIGH_FREQ
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bool
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default n
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help
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Select this for boards with a Voltage Regulator able to operate
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at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
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menu "HyperTransport setup"
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#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
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depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
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choice
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prompt "HyperTransport downlink width"
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default LIMIT_HT_DOWN_WIDTH_16
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help
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This option sets the maximum permissible HyperTransport
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downlink width.
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Use of this option will only limit the autodetected HT width.
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It will not (and cannot) increase the width beyond the autodetected
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limits.
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This is primarily used to work around poorly designed or laid out HT
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traces on certain motherboards.
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config LIMIT_HT_DOWN_WIDTH_8
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bool "8 bits"
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config LIMIT_HT_DOWN_WIDTH_16
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bool "16 bits"
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endchoice
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choice
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prompt "HyperTransport uplink width"
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default LIMIT_HT_UP_WIDTH_16
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help
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This option sets the maximum permissible HyperTransport
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uplink width.
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Use of this option will only limit the autodetected HT width.
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It will not (and cannot) increase the width beyond the autodetected
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limits.
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This is primarily used to work around poorly designed or laid out HT
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traces on certain motherboards.
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config LIMIT_HT_UP_WIDTH_8
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bool "8 bits"
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config LIMIT_HT_UP_WIDTH_16
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bool "16 bits"
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endchoice
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endmenu
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endif # NORTHBRIDGE_AMD_AMDFAM10
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