851ef96f4e
Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC; however, those ports were not declared as a resource. This had two major downsides: * It allowed the allocator to assign said ports to other devices * It required manually open up an IO window in the LPC bridge. The LPC bridge on many chromeec boards had to be painstakingly adjusted to meet these constraints. The advantage of declaring the resources upfront is that the lpc bridge can now scan its child resources and automatically open up IO windows, as requested by its LPC children devices. Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14585 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
126 lines
3.4 KiB
C
126 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include "ec.h"
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#include "ec_commands.h"
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enum {
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/* 8-bit access */
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ACCESS_TYPE_BYTE = 0x0,
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/* 16-bit access */
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ACCESS_TYPE_WORD = 0x1,
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/* 32-bit access */
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ACCESS_TYPE_LONG = 0x2,
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/*
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* 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the
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* EC data register to be incremented.
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*/
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ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3,
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};
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/* EMI registers are relative to base */
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#define MEC_EMI_HOST_TO_EC (MEC_EMI_BASE + 0)
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#define MEC_EMI_EC_TO_HOST (MEC_EMI_BASE + 1)
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#define MEC_EMI_EC_ADDRESS_B0 (MEC_EMI_BASE + 2)
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#define MEC_EMI_EC_ADDRESS_B1 (MEC_EMI_BASE + 3)
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#define MEC_EMI_EC_DATA_B0 (MEC_EMI_BASE + 4)
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#define MEC_EMI_EC_DATA_B1 (MEC_EMI_BASE + 5)
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#define MEC_EMI_EC_DATA_B2 (MEC_EMI_BASE + 6)
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#define MEC_EMI_EC_DATA_B3 (MEC_EMI_BASE + 7)
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/*
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* cros_ec_lpc_mec_emi_write_address
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*
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* Initialize EMI read / write at a given address.
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*
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* @addr: Starting read / write address
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* @access_mode: Type of access, typically 32-bit auto-increment
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*/
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static void mec_emi_write_address(u16 addr, u8 access_mode)
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{
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/* Address relative to start of EMI range */
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addr -= MEC_EMI_RANGE_START;
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outb((addr & 0xfc) | access_mode, MEC_EMI_EC_ADDRESS_B0);
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outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1);
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}
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/*
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* mec_io_bytes - Read / write bytes to MEC EMI port
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*
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* @write: 1 on write operation, 0 on read
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* @port: Base read / write address
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* @length: Number of bytes to read / write
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* @buf: Destination / source buffer
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* @csum: Optional parameter, sums data transferred
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*
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*/
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void mec_io_bytes(int write, u16 port, unsigned int length, u8 *buf, u8 *csum)
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{
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int i = 0;
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int io_addr;
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u8 access_mode, new_access_mode;
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if (length == 0)
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return;
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/*
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* Long access cannot be used on misaligned data since reading B0 loads
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* the data register and writing B3 flushes it.
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*/
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if ((port & 0x3) || (length < 4))
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access_mode = ACCESS_TYPE_BYTE;
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else
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access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT;
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/* Initialize I/O at desired address */
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mec_emi_write_address(port, access_mode);
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/* Skip bytes in case of misaligned port */
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io_addr = MEC_EMI_EC_DATA_B0 + (port & 0x3);
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while (i < length) {
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while (io_addr <= MEC_EMI_EC_DATA_B3) {
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if (write)
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outb(buf[i], io_addr++);
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else
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buf[i] = inb(io_addr++);
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if (csum)
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*csum += buf[i];
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port++;
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/* Extra bounds check in case of misaligned length */
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if (++i == length)
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return;
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}
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/*
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* Use long auto-increment access except for misaligned write,
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* since writing B3 triggers the flush.
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*/
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if (length - i < 4 && write)
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new_access_mode = ACCESS_TYPE_BYTE;
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else
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new_access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT;
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if (new_access_mode != access_mode ||
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access_mode != ACCESS_TYPE_LONG_AUTO_INCREMENT) {
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access_mode = new_access_mode;
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mec_emi_write_address(port, access_mode);
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}
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/* Access [B0, B3] on each loop pass */
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io_addr = MEC_EMI_EC_DATA_B0;
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}
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}
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