854bd492fc
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iae2dc0a934f0ea3ca59d8a811f1daeedb090a7bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
277 lines
8.3 KiB
Plaintext
277 lines
8.3 KiB
Plaintext
chip soc/intel/alderlake
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# FSP configuration
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register "eist_enable" = "1"
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# Sagv Configuration
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register "sagv" = "SaGv_Enabled"
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register "RMT" = "0"
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register "enable_c6dram" = "1"
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register "pmc_gpe0_dw0" = "GPP_J"
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register "pmc_gpe0_dw1" = "GPP_VPGIO"
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register "pmc_gpe0_dw2" = "GPD"
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# USB Configuration
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # USB-C LAN_USB1
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register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # MSI MYSTIC LIGHT
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register "usb2_ports[2]" = "USB2_PORT_MAX(OC0)" # USB-A LAN_USB1
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register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # JUSB5
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register "usb2_ports[4]" = "USB2_PORT_MAX(OC3)" # HUB to rear USB 2.0
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register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty?
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register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4
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register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4
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register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3
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register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3
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register "usb2_ports[10]" = "USB2_PORT_MAX(OC0)" # PS2_USB1
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register "usb2_ports[11]" = "USB2_PORT_MAX(OC0)" # PS2_USB1
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register "usb2_ports[12]" = "USB2_PORT_MAX(OC0)" # HUB to USB 2.0 headers
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register "usb2_ports[13]" = "USB2_PORT_MAX(OC6)" # CNVi BT
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
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register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
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register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
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register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
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register "usb3_ports[9]" = "USB3_PORT_EMPTY"
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# LPC generic I/O ranges
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register "gen1_dec" = "0x00fc0201"
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register "gen2_dec" = "0x003c0a01"
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register "gen3_dec" = "0x000c03f1"
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register "gen4_dec" = "0x000c0081"
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register "sata_salp_support" = "1"
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register "sata_ports_enable" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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[4] = 1,
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[5] = 1,
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[6] = 1,
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[7] = 1,
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}"
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register "sata_ports_dev_slp" = "{
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[0] = 0,
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[1] = 0,
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[2] = 0,
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[3] = 0,
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[4] = 0,
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[5] = 0,
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[6] = 1,
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[7] = 1,
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}"
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# HDMI on port B
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register "ddi_portB_config" = "1"
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register "ddi_ports_config" = "{
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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[DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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[DDI_PORT_2] = DDI_ENABLE_HPD,
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[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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[DDI_PORT_4] = DDI_ENABLE_HPD,
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}"
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register "hybrid_storage_mode" = "1"
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register "dmi_power_optimize_disable" = "1"
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# FIVR configuration
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register "fivr_rfi_frequency" = "1394"
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register "fivr_spread_spectrum" = "FIVR_SS_1_5"
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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}"
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device domain 0 on
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subsystemid 0x1462 0x7d25 inherit
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device ref pcie5_0 on
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register "cpu_pcie_rp[CPU_RP(2)]" = "{
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.clk_src = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong"
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"PCI_E1" "SlotDataBusWidth16X"
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end
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device ref pcie5_1 off end
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device ref igpu on end
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device ref pcie4_0 on
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_src = 9,
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.clk_req = 9,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
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"M2_1" "SlotDataBusWidth4X"
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end
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device ref crashlog off end
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device ref xhci on end
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device ref cnvi_wifi on
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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register "cnvi_bt_audio_offload" = "false"
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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register "enable_cnvi_ddr_rfim" = "true"
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device generic 0 on end
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end
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end
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device ref heci1 on end
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device ref heci2 off end
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device ref ide_r off end
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device ref kt off end
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device ref heci3 off end
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device ref heci4 off end
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device ref sata on end
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device ref pcie_rp1 on
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register "pch_pcie_rp[PCH_RP(1)]" = "{
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.clk_src = 10,
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.clk_req = 10,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort"
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"PCI_E2" "SlotDataBusWidth1X"
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end
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device ref pcie_rp2 on
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register "pch_pcie_rp[PCH_RP(2)]" = "{
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.clk_src = 17,
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.clk_req = 17,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
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"PCI_E4" "SlotDataBusWidth1X"
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end
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device ref pcie_rp3 on
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# i225 Ethernet, Clock PM unsupported, onboard device
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register "pch_pcie_rp[PCH_RP(3)]" = "{
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.clk_src = 12,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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end
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device ref pcie_rp4 off end
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device ref pcie_rp5 on
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 15,
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.clk_req = 15,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
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"PCI_E3" "SlotDataBusWidth4X"
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end
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device ref pcie_rp9 on
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 13,
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.clk_req = 13,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
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"M2_3" "SlotDataBusWidth4X"
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end
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# These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports.
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# There is an ASMedia switch on-board to mux the SATA ports 7, 8 and PCIe
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# 9-12, 21-24 to M2_3 and M2_4 slots
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device ref pcie_rp13 off end
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device ref pcie_rp14 off end
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device ref pcie_rp15 off end
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device ref pcie_rp16 off end
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device ref pcie_rp17 off end
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device ref pcie_rp18 off end
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device ref pcie_rp19 off end
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device ref pcie_rp20 off end
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device ref pcie_rp21 on
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register "pch_pcie_rp[PCH_RP(21)]" = "{
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.clk_src = 14,
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.clk_req = 14,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
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"M2_4" "SlotDataBusWidth4X"
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end
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device ref pcie_rp25 on
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register "pch_pcie_rp[PCH_RP(25)]" = "{
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.clk_src = 8,
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.clk_req = 8,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
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.PcieRpL1Substates = L1_SS_L1_2,
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.pcie_rp_aspm = ASPM_L0S_L1,
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}"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
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"M2_2" "SlotDataBusWidth4X"
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end
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device ref pch_espi on
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chip superio/nuvoton/nct6687d
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device pnp 4e.1 off end # Parallel port
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device pnp 4e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.3 off end # COM2, IR
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device pnp 4e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 4e.6 off end # CIR
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device pnp 4e.7 off end # GPIO0-7
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device pnp 4e.8 off end # P80 UART
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device pnp 4e.9 off end # GPIO8-9, GPIO1-8 AF
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device pnp 4e.a on # ACPI
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# Vendor firmware did not assign I/O and IRQ
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end
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device pnp 4e.b on # EC
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io 0x60 = 0xa20
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# Vendor firmware did not assign IRQ
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end
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device pnp 4e.c off end # RTC
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device pnp 4e.d off end # Deep Sleep
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device pnp 4e.e off end # TACH/PWM assignment
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device pnp 4e.f off end # Function register
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end
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end
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device ref p2sb on end
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device ref hda on
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subsystemid 0x1462 0x9d25
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register "pch_hda_audio_link_hda_enable" = "1"
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register "pch_hda_dsp_enable" = "0"
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register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
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register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
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register "pch_hda_idisp_codec_enable" = "true"
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end
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device ref smbus on end
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chip drivers/crb
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device mmio 0xfed40000 on end
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end
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end
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end
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