855224bb28
coreboot used to set the chipset to IDE mode unconditionally. Now, the user has a couple of ways to choose the configuration: - If a CMOS variable sata_mode exist, it is used to decide if IDE or AHCI is to be used as interface. - If not, a Kconfig option is used. - If unchanged, the Kconfig option is set to IDE. So unless the cmos.layout is extended or Kconfig is modified, this won't change behaviour. [Patrick: Compared to Josef's version, I changed the Kconfig option to be boolean, instead of a magic string. Also, the "IDE" default is handled in Kconfig, instead of an additional line of code.] Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
278 lines
8.0 KiB
C
278 lines
8.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2008 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <delay.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include "sb600.h"
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#include <pc80/mc146818rtc.h>
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#define SATA_MODE_IDE 1
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#define SATA_MODE_AHCI 0
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static int sata_drive_detect(int portnum, u16 iobar)
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{
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u8 byte, byte2;
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int i = 0;
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outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
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while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
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(byte != (0xA0 + 0x10 * (portnum % 2))) ||
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((byte2 & 0x88) != 0)) {
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printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
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if (byte != (0xA0 + 0x10 * (portnum % 2))) {
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/* This will happen at the first iteration of this loop
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* if the first SATA port is unpopulated and the
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* second SATA port is populated.
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*/
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printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
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"retrying init\n", i * 10);
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return 1;
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} else
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printk(BIOS_SPEW, "drive detection not yet completed, "
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"waiting...\n");
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mdelay(10);
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i++;
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}
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printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
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return 0;
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}
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static void sata_init(struct device *dev)
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{
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u8 byte;
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u16 word;
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u32 dword;
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u32 sata_bar5;
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u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
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int i, j;
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struct southbridge_ati_sb600_config *conf;
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conf = dev->chip_info;
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device_t sm_dev;
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/* SATA SMBus Disable */
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/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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/* Disable SATA SMBUS */
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byte = pci_read_config8(sm_dev, 0xad);
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byte |= (1 << 1);
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/* Enable SATA and power saving */
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byte = pci_read_config8(sm_dev, 0xad);
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byte |= (1 << 0);
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byte |= (1 << 5);
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pci_write_config8(sm_dev, 0xad, byte);
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/* Set the interrupt Mapping to INTG# */
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byte = pci_read_config8(sm_dev, 0xaf);
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byte = 0x6 << 2;
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pci_write_config8(sm_dev, 0xaf, byte);
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/* get base address */
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sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
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sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
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sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
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sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
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sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
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sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
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printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */
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printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */
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printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
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printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
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printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
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printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
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/* SERR-Enable */
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word = pci_read_config16(dev, 0x04);
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word |= (1 << 8);
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pci_write_config16(dev, 0x04, word);
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/* Dynamic power saving */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 2);
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pci_write_config8(dev, 0x40, byte);
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/* Set SATA Operation Mode */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 0);
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byte |= (1 << 4);
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pci_write_config8(dev, 0x40, byte);
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// 1 means IDE, 0 means AHCI
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if( get_option(&i, "sata_mode") < 0 ) {
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// no cmos option
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i = CONFIG_SATA_MODE;
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}
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printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" );
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dword = pci_read_config32(dev, 0x8);
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dword &= 0xff0000ff;
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if (i == SATA_MODE_IDE)
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dword |= 0x00018f00; // IDE mode
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else
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dword |= 0x00060100; // AHCI mode
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pci_write_config32(dev, 0x8, dword);
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byte = pci_read_config8(dev, 0x40);
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byte &= ~(1 << 0);
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pci_write_config8(dev, 0x40, byte);
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/* Enable the SATA watchdog counter */
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byte = pci_read_config8(dev, 0x44);
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byte |= (1 << 0);
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pci_write_config8(dev, 0x44, byte);
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/* Program the watchdog counter to 0x10 */
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byte = 0x10;
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pci_write_config8(dev, 0x46, byte);
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/* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */
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word = 0x2c00;
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pci_write_config16(dev, 0x86, word);
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/* RPR6.5 Program the Phy Tuning4Ports */
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dword = 0x00B401D6;
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pci_write_config32(dev, 0x88, dword);
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pci_write_config32(dev, 0x8c, dword);
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pci_write_config32(dev, 0x90, dword);
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pci_write_config32(dev, 0x94, dword);
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byte = 0xB8;
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pci_write_config8(dev, 0xA5, byte);
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pci_write_config8(dev, 0xAD, byte);
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pci_write_config8(dev, 0xB5, byte);
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pci_write_config8(dev, 0xBD, byte);
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/* RPR 6.8 */
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word = pci_read_config16(dev, 0x42);
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word |= 1 << 7;
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pci_write_config16(dev, 0x42, word);
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/* RPR 6.9 */
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dword = pci_read_config32(dev, 0x40);
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dword |= 1 << 25;
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pci_write_config32(dev, 0x40, dword);
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/* Enable the I/O, MM, BusMaster access for SATA */
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byte = pci_read_config8(dev, 0x4);
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byte |= 7 << 0;
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pci_write_config8(dev, 0x4, byte);
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/* RPR6.6 SATA drive detection. */
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/* Use BAR5+0x128,BAR0 for Primary Slave */
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/* Use BAR5+0x1A8,BAR0 for Primary Slave */
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/* Use BAR5+0x228,BAR2 for Secondary Master */
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/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
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for (i = 0; i < 4; i++) {
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byte = read8(sata_bar5 + 0x128 + 0x80 * i);
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printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
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byte &= 0xF;
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if( byte == 0x1 ) {
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/* If the drive status is 0x1 then we see it but we aren't talking to it. */
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/* Try to do something about it. */
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printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
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/* Read in Port-N Serial ATA Control Register */
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byte = read8(sata_bar5 + 0x12C + 0x80 * i);
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/* Set Reset Bit and 1.5g bit */
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byte |= 0x11;
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write8((sata_bar5 + 0x12C + 0x80 * i), byte);
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/* Wait 1ms */
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mdelay(1);
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/* Clear Reset Bit */
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byte &= ~0x01;
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write8((sata_bar5 + 0x12C + 0x80 * i), byte);
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/* Wait 1ms */
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mdelay(1);
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/* Reread status */
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byte = read8(sata_bar5 + 0x128 + 0x80 * i);
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printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
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byte &= 0xF;
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}
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if (byte == 0x3) {
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for (j = 0; j < 10; j++) {
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if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
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break;
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}
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printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
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(i / 2) ? "Secondary" : "Primary",
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(i % 2 ) ? "Slave" : "Master",
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(j == 10) ? "not " : "",
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(j == 10) ? j : j + 1);
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} else {
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printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
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(i / 2) ? "Secondary" : "Primary",
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(i % 2 ) ? "Slave" : "Master", i);
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}
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}
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/* Below is CIM InitSataLateFar */
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/* Enable interrupts from the HBA */
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byte = read8(sata_bar5 + 0x4);
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byte |= 1 << 1;
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write8((sata_bar5 + 0x4), byte);
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/* Clear error status */
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write32((sata_bar5 + 0x130), 0xFFFFFFFF);
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write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
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write32((sata_bar5 + 0x230), 0xFFFFFFFF);
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write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
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/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
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/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
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/* word = 0x0000; */
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/* word = pm_ioread(0x28); */
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/* byte = pm_ioread(0x29); */
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/* word |= byte<<8; */
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/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
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/* write32(word, 0x80000000); */
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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/* .enable = sb600_enable, */
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.init = sata_init,
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.scan_bus = 0,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver sata0_driver __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_SB600_SATA,
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};
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