This patch adds a new utility for converting a pad configuration from the inteltool dump to the PAD_CFG_*() macros [1] for coreboot and GPIO config data structures for FSP/sdk2-platforms/slimbootloader [2,3]. Mirror: https://github.com/maxpoliak/pch-pads-parser.git [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] https://slimbootloader.github.io/tools/index.html#gpio-tool [3] 3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35643 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
		
			
				
	
	
		
			279 lines
		
	
	
		
			8.3 KiB
		
	
	
	
		
			Go
		
	
	
	
	
	
			
		
		
	
	
			279 lines
		
	
	
		
			8.3 KiB
		
	
	
	
		
			Go
		
	
	
	
	
	
| package snr
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| 
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| import "strings"
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| import "fmt"
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| 
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| // Local packages
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| import "../common"
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| import "../../config"
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| import "../../fields"
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| 
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| const (
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| 	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
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| 	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
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| )
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| 
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| const (
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| 	PAD_CFG_DW0 = common.PAD_CFG_DW0
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| 	PAD_CFG_DW1 = common.PAD_CFG_DW1
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| 	MAX_DW_NUM  = common.MAX_DW_NUM
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| )
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| 
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| type PlatformSpecific struct {}
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| 
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| // RemmapRstSrc - remmap Pad Reset Source Config
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| func (PlatformSpecific) RemmapRstSrc() {
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| 	macro := common.GetMacro()
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| 	if config.TemplateGet() != config.TempInteltool {
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| 		// Use reset source remapping only if the input file is inteltool.log dump
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| 		return
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| 	}
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| 	if strings.Contains(macro.PadIdGet(), "GPD") {
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| 		// See reset map for the Sunrise GPD Group in the Community 2:
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| 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/gpio.c#L15
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| 		// remmap is not required because it is the same as common.
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| 		return
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| 	}
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| 
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| 	dw0 := macro.Register(PAD_CFG_DW0)
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| 	var remapping = map[uint8]uint32{
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| 		0: common.RST_RSMRST << common.PadRstCfgShift,
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| 		1: common.RST_DEEP   << common.PadRstCfgShift,
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| 		2: common.RST_PLTRST << common.PadRstCfgShift,
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| 	}
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| 	resetsrc, valid := remapping[dw0.GetResetConfig()]
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| 	if valid {
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| 		// dw0.SetResetConfig(resetsrc)
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| 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
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| 		dw0.ValueSet(ResetConfigFieldVal)
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| 	} else {
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| 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
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| 	}
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| 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
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| }
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| 
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| // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
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| // as a new argument
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| func (PlatformSpecific) Pull() {
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| 	macro := common.GetMacro()
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| 	dw1 := macro.Register(PAD_CFG_DW1)
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| 	var pull = map[uint8]string{
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| 		0x0: "NONE",
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| 		0x2: "5K_PD",
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| 		0x4: "20K_PD",
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| 		0x9: "1K_PU",
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| 		0xa: "5K_PU",
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| 		0xb: "2K_PU",
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| 		0xc: "20K_PU",
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| 		0xd: "667_PU",
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| 		0xf: "NATIVE",
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| 	}
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| 	str, valid := pull[dw1.GetTermination()]
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| 	if !valid {
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| 		str = "INVALID"
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| 		fmt.Println("Error",
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| 				macro.PadIdGet(),
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| 				" invalid TERM value = ",
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| 				int(dw1.GetTermination()))
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| 	}
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| 	macro.Separator().Add(str)
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| }
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| 
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| // Generate macro to cause peripheral IRQ when configured in GPIO input mode
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| func ioApicRoute() bool {
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| 	macro := common.GetMacro()
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| 	dw0 := macro.Register(PAD_CFG_DW0)
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| 	if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
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| 		return false
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| 	}
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| 
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| 	macro.Add("_APIC")
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| 	if dw0.GetRXLevelEdgeConfiguration() == common.TRIG_LEVEL {
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| 		if dw0.GetRxInvert() != 0 {
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| 			// PAD_CFG_GPI_APIC_INVERT(pad, pull, rst)
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| 			macro.Add("_INVERT")
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| 		}
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| 		// PAD_CFG_GPI_APIC(pad, pull, rst)
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| 		macro.Add("(").Id().Pull().Rstsrc().Add("),")
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| 		return true
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| 	}
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| 
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| 	// e.g. PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm)
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| 	macro.Add("_IOS(").Id().Pull().Rstsrc().Trig().Invert().Add(", TxLASTRxE, SAME),")
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| 	return true
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| }
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| 
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| // Generate macro to cause NMI when configured in GPIO input mode
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| func nmiRoute() bool {
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| 	macro := common.GetMacro()
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| 	if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 {
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| 		return false
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| 	}
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| 	// PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
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| 	macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
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| 	return true
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| }
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| 
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| // Generate macro to cause SCI when configured in GPIO input mode
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| func sciRoute() bool {
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| 	macro := common.GetMacro()
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| 	dw0 := macro.Register(PAD_CFG_DW0)
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| 	if dw0.GetGPIOInputRouteSCI() == 0 {
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| 		return false
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| 	}
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| 	// e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
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| 	if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 {
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| 		// e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES),
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| 		// #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv)	\
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| 		//             PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv)
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| 		macro.Add("_ACPI")
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| 	}
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| 	macro.Add("_SCI").Add("(").Id().Pull().Rstsrc()
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| 	if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 {
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| 		macro.Trig()
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| 	}
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| 	macro.Invert().Add("),")
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| 	return true
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| }
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| 
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| // Generate macro to cause SMI when configured in GPIO input mode
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| func smiRoute() bool {
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| 	macro := common.GetMacro()
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| 	dw0 := macro.Register(PAD_CFG_DW0)
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| 	if dw0.GetGPIOInputRouteSMI() == 0 {
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| 		return false
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| 	}
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| 	if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 {
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| 		// e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES),
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| 		macro.Add("_ACPI")
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| 	}
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| 	macro.Add("_SMI").Add("(").Id().Pull().Rstsrc()
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| 	if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 {
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| 		// e.g. PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE),
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| 		macro.Trig()
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| 	}
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| 	macro.Invert().Add("),")
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| 	return true
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| }
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| 
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| // Adds PAD_CFG_GPI macro with arguments
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| func (PlatformSpecific) GpiMacroAdd() {
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| 	macro := common.GetMacro()
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| 	var ids []string
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| 	macro.Set("PAD_CFG_GPI")
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| 	for routeid, isRoute := range map[string]func() (bool) {
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| 		"IOAPIC": ioApicRoute,
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| 		"SCI":    sciRoute,
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| 		"SMI":    smiRoute,
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| 		"NMI":    nmiRoute,
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| 	} {
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| 		if isRoute() {
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| 			ids = append(ids, routeid)
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| 		}
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| 	}
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| 
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| 	switch argc := len(ids); argc {
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| 	case 0:
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| 		// e.g. PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own)
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| 		macro.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),")
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| 	case 1:
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| 		// GPI with IRQ route
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| 		if config.AreFieldsIgnored() {
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| 			// Set Host Software Ownership to ACPI mode
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| 			macro.SetPadOwnership(common.PAD_OWN_ACPI)
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| 		}
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| 
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| 	case 2:
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| 		// PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2)
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| 		macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
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| 		macro.Add(", " + ids[0] + ", " + ids[1] + "),")
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| 		if config.AreFieldsIgnored() {
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| 			// Set Host Software Ownership to ACPI mode
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| 			macro.SetPadOwnership(common.PAD_OWN_ACPI)
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| 		}
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| 	default:
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| 		// Clear the control mask so that the check fails and "Advanced" macro is
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| 		// generated
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| 		macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
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| 	}
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| }
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| 
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| // Adds PAD_CFG_GPO macro with arguments
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| func (PlatformSpecific) GpoMacroAdd() {
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| 	macro := common.GetMacro()
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| 	dw0 := macro.Register(PAD_CFG_DW0)
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| 	term := macro.Register(PAD_CFG_DW1).GetTermination()
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| 
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| 	// #define PAD_CFG_GPO(pad, val, rst)                \
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| 	//    _PAD_CFG_STRUCT(pad,                           \
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| 	//      PAD_FUNC(GPIO) | PAD_RESET(rst) |            \
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| 	//      PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
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| 	//      PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
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| 	if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
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| 		dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
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| 	}
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| 	macro.Set("PAD_CFG")
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| 	if macro.IsOwnershipDriver() {
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| 		// PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull)
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| 		macro.Add("_GPO_GPIO_DRIVER").Add("(").Id().Val().Rstsrc().Pull().Add("),")
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| 		return
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| 	}
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| 	if term != 0 {
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| 		// e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
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| 		macro.Add("_TERM")
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| 	}
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| 	macro.Add("_GPO").Add("(").Id().Val()
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| 	if term != 0 {
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| 		macro.Pull()
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| 	}
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| 	macro.Rstsrc().Add("),")
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| }
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| 
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| // Adds PAD_CFG_NF macro with arguments
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| func (PlatformSpecific) NativeFunctionMacroAdd() {
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| 	macro := common.GetMacro()
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| 	// e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1)
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| 	macro.Set("PAD_CFG_NF")
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| 	if macro.Register(PAD_CFG_DW1).GetPadTol() != 0 {
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| 		macro.Add("_1V8")
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| 	}
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| 	macro.Add("(").Id().Pull().Rstsrc().Padfn().Add("),")
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| }
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| 
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| // Adds PAD_NC macro
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| func (PlatformSpecific) NoConnMacroAdd() {
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| 	macro := common.GetMacro()
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| 	// #define PAD_NC(pad, pull)
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| 	// _PAD_CFG_STRUCT(pad,
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| 	//     PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
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| 	//     PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)),
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| 	dw0 := macro.Register(PAD_CFG_DW0)
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| 
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| 	// Some fields of the configuration registers are hidden inside the macros,
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| 	// we should check them to update the corresponding bits in the control mask.
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| 	if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
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| 		dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
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| 	}
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| 	if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP
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| 		dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
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| 	}
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| 
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| 	macro.Set("PAD_NC").Add("(").Id().Pull().Add("),")
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| }
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| 
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| // GenMacro - generate pad macro
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| // dw0 : DW0 config register value
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| // dw1 : DW1 config register value
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| // return: string of macro
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| //         error
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| func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
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| 	macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet())
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| 	macro.Clear()
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| 	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
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| 	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
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| 	macro.PadIdSet(id).SetPadOwnership(ownership)
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| 	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
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| 	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
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| 	return macro.Generate()
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| }
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