86091f94b6
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
80 lines
2.3 KiB
C
80 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <arch/io.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <soc/iosf.h>
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#include <cpu/intel/microcode/microcode.c>
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static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
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{
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msr_t basem, maskm;
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basem.lo = base | type;
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basem.hi = 0;
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wrmsr(MTRR_PHYS_BASE(reg), basem);
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maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
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maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
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wrmsr(MTRR_PHYS_MASK(reg), maskm);
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}
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static void enable_rom_caching(void)
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{
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msr_t msr;
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disable_cache();
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/* Why only top 4MiB ? */
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set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
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enable_cache();
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/* Enable Variable MTRRs */
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msr.hi = 0x00000000;
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msr.lo = 0x00000800;
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wrmsr(MTRR_DEF_TYPE_MSR, msr);
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}
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static void setup_mmconfig(void)
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{
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uint32_t reg;
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/* Set up the MMCONF range. The register lives in the BUNIT. The
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* IO variant of the config access needs to be used initially to
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* properly configure as the IOSF access registers live in PCI
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* config space. */
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reg = 0;
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/* Clear the extended register. */
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pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
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reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
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pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
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reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
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IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
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pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
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}
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static void bootblock_cpu_init(void)
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{
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/* Allow memory-mapped PCI config access. */
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setup_mmconfig();
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/* Load microcode before any caching. */
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intel_update_microcode_from_cbfs();
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enable_rom_caching();
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}
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