8702ab5ab1
fix some PCI IDs, enable USB bus mastering, add some license headers, ... LPC code needs another look, but I think we're getting there. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
253 lines
6.8 KiB
C
253 lines
6.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Linux Networx
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* Copyright (C) 2004 SuSE Linux AG
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* Copyright (C) 2004 Tyan Computer
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <arch/io.h>
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#include "i82801dx.h"
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#define NMI_OFF 0
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void i82801dx_enable_ioapic(struct device *dev)
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{
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u32 dword;
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volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000;
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volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010;
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dword = pci_read_config32(dev, GEN_CNTL);
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dword |= (3 << 7); /* enable ioapic */
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dword |= (1 << 13); /* coprocessor error enable */
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dword |= (1 << 1); /* delay transaction enable */
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dword |= (1 << 2); /* DMA collection buf enable */
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pci_write_config32(dev, GEN_CNTL, dword);
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printk_debug("ioapic southbridge enabled %x\n", dword);
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*ioapic_sba = 0;
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*ioapic_sbd = (2 << 24);
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//lyh *ioapic_sba=3;
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//lyh *ioapic_sbd=1;
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*ioapic_sba = 0;
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dword = *ioapic_sbd;
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printk_debug("Southbridge apic id = %x\n", dword);
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if (dword != (2 << 24))
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die("");
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//lyh *ioapic_sba=3;
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//lyh dword=*ioapic_sbd;
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//lyh printk_debug("Southbridge apic DT = %x\n",dword);
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//lyh if(dword!=1)
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//lyh die("");
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}
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void i82801dx_enable_serial_irqs(struct device *dev)
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{
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
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}
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void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
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{
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u16 word;
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int i;
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word = pci_read_config16(dev, PCI_DMA_CFG);
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word &= ((1 << 10) - (1 << 8));
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for (i = 0; i < 8; i++) {
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if (i == 4)
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continue;
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word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
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}
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pci_write_config16(dev, PCI_DMA_CFG, word);
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}
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void i82801dx_rtc_init(struct device *dev)
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{
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u8 byte;
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u32 dword;
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int rtc_failed;
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byte = pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = byte & RTC_FAILED;
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if (rtc_failed) {
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byte &= ~(1 << 1); /* preserve the power fail state */
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pci_write_config8(dev, GEN_PMCON_3, byte);
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}
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dword = pci_read_config32(dev, GEN_STS);
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rtc_failed |= dword & (1 << 2);
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rtc_init(rtc_failed);
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}
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void i82801dx_1f0_misc(struct device *dev)
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{
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pci_write_config16(dev, PCICMD, 0x014f);
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pci_write_config32(dev, PMBASE, 0x00001001);
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pci_write_config8(dev, ACPI_CNTL, 0x10);
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pci_write_config32(dev, GPIO_BASE, 0x00001181);
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pci_write_config8(dev, GPIO_CNTL, 0x10);
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pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
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pci_write_config8(dev, PIRQE_ROUT, 0x07);
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pci_write_config8(dev, RTC_CONF, 0x04);
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pci_write_config8(dev, COM_DEC, 0x10); //lyh E0->
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pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D->
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}
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static void enable_hpet(struct device *dev)
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{
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const unsigned long hpet_address = 0xfed0000;
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u32 dword;
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u32 code = (0 & 0x3);
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dword = pci_read_config32(dev, GEN_CNTL);
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dword |= (1 << 17); /* enable hpet */
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/*Bits [16:15]Memory Address Range
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00 FED0_0000h - FED0_03FFh
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01 FED0_1000h - FED0_13FFh
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10 FED0_2000h - FED0_23FFh
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11 FED0_3000h - FED0_33FFh */
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dword &= ~(3 << 15); /* clear it */
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dword |= (code << 15);
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printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12));
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}
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static void lpc_init(struct device *dev)
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{
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u8 byte;
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int pwr_on = -1;
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int nmi_option;
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/* IO APIC initialization */
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i82801dx_enable_ioapic(dev);
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i82801dx_enable_serial_irqs(dev);
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#ifdef SUSPICIOUS_LOOKING_CODE
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// The ICH-4 datasheet does not mention this configuration register.
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// This code may have been inherited (incorrectly) from code for the AMD 766 southbridge,
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// which *does* support this functionality.
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/* posted memory write enable */
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byte = pci_read_config8(dev, 0x46);
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pci_write_config8(dev, 0x46, byte | (1 << 0));
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#endif
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/* power after power fail */
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/* FIXME this doesn't work! */
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*/
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pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
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printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
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#if 0
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/* Enable Error reporting */
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/* Set up sync flood detected */
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byte = pci_read_config8(dev, 0x47);
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byte |= (1 << 1);
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pci_write_config8(dev, 0x47, byte);
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#endif
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/* Set up NMI on errors */
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byte = inb(0x61);
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byte &= ~(1 << 3); /* IOCHK# NMI Enable */
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byte &= ~(1 << 2); /* PCI SERR# Enable */
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outb(byte, 0x61);
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byte = inb(0x70);
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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byte &= ~(1 << 7); /* set NMI */
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outb(byte, 0x70);
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}
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/* Initialize the real time clock */
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i82801dx_rtc_init(dev);
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i82801dx_lpc_route_dma(dev, 0xff);
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/* Initialize isa dma */
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isa_dma_init();
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i82801dx_1f0_misc(dev);
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/* Initialize the High Precision Event Timers */
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enable_hpet(dev);
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}
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static void i82801dx_lpc_read_resources(device_t dev)
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{
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struct resource *res;
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add an extra subtractive resource for both memory and I/O. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->base = 0;
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res->size = 0x1000;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->base = 0xff800000;
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res->size = 0x00800000; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 3); /* IOAPIC */
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res->base = 0xfec00000;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static void i82801dx_lpc_enable_resources(device_t dev)
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{
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pci_dev_enable_resources(dev);
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enable_childrens_resources(dev);
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}
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static struct device_operations lpc_ops = {
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.read_resources = i82801dx_lpc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = i82801dx_lpc_enable_resources,
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.init = lpc_init,
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.scan_bus = scan_static_bus,
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.enable = i82801dx_enable,
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};
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/* 82801DB/DBL */
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static const struct pci_driver lpc_driver_db __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
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};
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/* 82801DBM */
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static const struct pci_driver lpc_driver_dbm __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,
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};
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