88bc0f1604
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
231 lines
6.9 KiB
Plaintext
231 lines
6.9 KiB
Plaintext
chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
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register "s0ix_enable" = true
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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register "eist_enable" = "1"
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# Disable DPTF
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register "dptf_enable" = "0"
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register "tcc_offset" = "5" # TCC of 95C
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# FSP Configuration
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register "DspEnable" = "0"
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register "IoBufferOwnership" = "0"
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register "SkipExtGfxScan" = "1"
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register "SaGv" = "SaGv_Enabled"
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register "IslVrCmd" = "2"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "4" # 4s
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------+-------+
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#| Domain/Setting | SA | IA | GTUS | GTS |
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#+----------------+-------+-------+-------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
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#| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
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#+----------------+-------+-------+-------+-------+
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#Note: IccMax settings are moved to SoC code
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart0] = PchSerialIoDisabled,
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[PchSerialIoIndexUart1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart2] = PchSerialIoDisabled,
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}"
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device domain 0 on
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device ref igpu on end
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device ref south_xhci on
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register "usb2_ports" = "{
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[0] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
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[1] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
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[2] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
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[3] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
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[4] = USB2_PORT_SHORT(OC_SKIP), // Type-A Port
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[5] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
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[6] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
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[7] = USB2_PORT_SHORT(OC_SKIP), // mPCIe slot
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}"
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register "usb3_ports" = "{
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[0] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
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[1] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
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[2] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
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[3] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
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}"
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end
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device ref heci1 on end
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device ref sata on
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register "SataPortsEnable" = "{
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[0] = 1,
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[1] = 1,
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}"
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end
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device ref pcie_rp1 on
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# LAN
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register "PcieRpEnable[0]" = "1"
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register "PcieRpAdvancedErrorReporting[0]" = "1"
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register "PcieRpLtrEnable[0]" = "1"
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register "PcieRpClkSrcNumber[0]" = "0"
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end
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device ref pcie_rp2 on
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# LAN
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register "PcieRpEnable[1]" = "1"
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register "PcieRpAdvancedErrorReporting[1]" = "1"
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register "PcieRpLtrEnable[1]" = "1"
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register "PcieRpClkSrcNumber[1]" = "1"
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end
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device ref pcie_rp3 on
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# LAN
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register "PcieRpEnable[2]" = "1"
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register "PcieRpAdvancedErrorReporting[2]" = "1"
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register "PcieRpLtrEnable[2]" = "1"
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register "PcieRpClkSrcNumber[2]" = "2"
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end
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device ref pcie_rp4 on
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# LAN
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register "PcieRpEnable[3]" = "1"
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register "PcieRpAdvancedErrorReporting[3]" = "1"
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register "PcieRpLtrEnable[3]" = "1"
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register "PcieRpClkSrcNumber[3]" = "3"
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end
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device ref pcie_rp5 on
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# LAN
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register "PcieRpEnable[4]" = "1"
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpClkSrcNumber[4]" = "4"
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end
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device ref pcie_rp6 on
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# LAN
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register "PcieRpEnable[5]" = "1"
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieRpClkSrcNumber[5]" = "5"
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end
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device ref pcie_rp9 on
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# mPCIe WIFI
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register "PcieRpEnable[8]" = "1"
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register "PcieRpAdvancedErrorReporting[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieRpClkSrcNumber[8]" = "5"
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register "PcieRpClkReqSupport[8]" = "1"
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register "PcieRpClkReqNumber[8]" = "0"
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smbios_slot_desc
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"SlotTypePciExpressMini52pinWithoutBSKO"
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"SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
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end
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device ref lpc_espi on
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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register "gen1_dec" = "0x00fc0201"
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register "gen2_dec" = "0x007c0a01"
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register "gen3_dec" = "0x000c03e1"
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register "gen4_dec" = "0x001c02e1"
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chip superio/ite/it8772f
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register "TMPIN1.mode" = "THERMAL_RESISTOR"
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register "TMPIN2.mode" = "THERMAL_RESISTOR"
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register "TMPIN3.mode" = "THERMAL_PECI"
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# FAN2 available on fan header but unused
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device pnp 2e.0 off end # FDC
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device pnp 2e.1 on # Serial Port 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 on # Environment Controller
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io 0x60 = 0xa40
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io 0x62 = 0xa30
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irq 0x70 = 9
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end
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device pnp 2e.5 off end # Keyboard
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device pnp 2e.6 off end # Mouse
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device pnp 2e.7 off end # GPIO
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device pnp 2e.a off end # IR
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end
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end
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device ref smbus on end
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end
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chip drivers/crb
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device mmio 0xfed40000 on end
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end
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end
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