894f19bdf6
Found using 'Wmissing-include-dirs' command option. Change-Id: Ie079dcf8c1e662ce6ef068befa43dfe90c89edd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70395 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
73 lines
2.0 KiB
Makefile
73 lines
2.0 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
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subdirs-y += romstage
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bootblock-y += bootblock/esram_init.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += i2c.c
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bootblock-y += reg_access.c
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bootblock-y += tsc_freq.c
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bootblock-y += uart_common.c
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verstage-y += i2c.c
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verstage-y += reg_access.c
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verstage-y += tsc_freq.c
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verstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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romstage-y += i2c.c
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romstage-y += memmap.c
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romstage-y += reg_access.c
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romstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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romstage-y += tsc_freq.c
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romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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romstage-y += reset.c
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postcar-y += fsp_params.c
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postcar-y += i2c.c
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postcar-y += reg_access.c
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postcar-y += tsc_freq.c
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postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += ehci.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio_i2c.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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ramstage-y += northcluster.c
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ramstage-y += reg_access.c
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ramstage-y += reset.c
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ramstage-y += sd.c
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ramstage-y += spi.c
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ramstage-y += spi_debug.c
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ramstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/quark
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CPPFLAGS_common += -I$(src)/soc/intel/quark/include
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# Chipset microcode path
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CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
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# Since FSP-M runs in CAR we need to relocate it to a specific address
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$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_ESRAM_LOC)
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# Add the FSP binary to the CBFS image
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cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
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fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
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fsp.bin-position := $(CONFIG_FSP_LOC)
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fsp.bin-type := raw
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# Add the chipset microcode file to the CBFS image
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cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
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rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
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rmu.bin-position := $(CONFIG_RMU_LOC)
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rmu.bin-type := raw
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endif # CONFIG_SOC_INTEL_QUARK
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