8aaa00401b
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).
This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.
Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/24924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include "pch.h"
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#include <southbridge/intel/common/rcba.h>
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#include "northbridge/intel/sandybridge/sandybridge.h"
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void
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southbridge_configure_default_intmap(void)
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{
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P1IP SLOT1 INTA -> PIRQB
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* D28IP_P2IP SLOT2 INTB -> PIRQF
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* D28IP_P3IP SLOT3 INTC -> PIRQD
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* D28IP_P5IP SLOT5 INTC -> PIRQD
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* D29IP_E1P EHCI1 INTA -> PIRQD
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* D26IP_E2P EHCI2 INTA -> PIRQF
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* D31IP_SIP SATA INTA -> PIRQB (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQH
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* D31IP_TTIP THRT INTC -> PIRQA
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* D27IP_ZIP HDA INTA -> PIRQA (MSI)
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*
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*/
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RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
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(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
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RCBA32(D30IP) = (NOINT << D30IP_PIP);
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RCBA32(D29IP) = (INTA << D29IP_E1P);
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RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
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(INTC << D28IP_P3IP) | (INTC << D28IP_P5IP);
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RCBA32(D27IP) = (INTA << D27IP_ZIP);
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RCBA32(D26IP) = (INTA << D26IP_E2P);
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RCBA32(D25IP) = (NOINT << D25IP_LIP);
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RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
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/* Device interrupt route registers */
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DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
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DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
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DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
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DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
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DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
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DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
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/* Enable IOAPIC (generic) */
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RCBA16(EOIC) = 0x0100;
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/* PCH BWG says to read back the IOAPIC enable register */
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(void) RCBA16(EOIC);
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}
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void
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southbridge_rcba_config(void)
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{
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RCBA32(FD) = PCH_DISABLE_ALWAYS;
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}
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