8ada1526df
e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
175 lines
4.9 KiB
C
175 lines
4.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _RD890_CFG_H_
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#define _RD890_CFG_H_
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#include "NbPlatform.h"
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/* platform dependent configuration default value */
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/**
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* Path from CPU to NB
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* [0..7] - Node (0..8)
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* [8..11] - Link (0..3)
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* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
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*/
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#ifndef DEFAULT_HT_PATH
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#if CONFIG_CPU_AMD_AGESA_FAMILY10
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#define DEFAULT_HT_PATH {0x0, 0x3}
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#endif
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#if CONFIG_CPU_AMD_AGESA_FAMILY15
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#define DEFAULT_HT_PATH {0x0, 0x1}
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#endif
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#endif
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/**
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* Bitmap of enabled ports on NB #0/1/2/3
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* Bit[0] - Reserved
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* Bit[1] - Reserved
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* Bit[2] - Enable PCIe port 2
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* Bit[3] - Enable PCIe port 3
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* Bit[4] - Enable PCIe port 4
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* Bit[5] - Enable PCIe port 5
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* Bit[6] - Enable PCIe port 2
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* Bit[7] - Enable PCIe port 7
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* Bit[8] - Reserved
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* Bit[9] - Enable PCIe port 9
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* Bit[10]- Enable PCIe port 10
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* Bit[11]- Enable PCIe port 11
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* Bit[12]- Enable PCIe port 12
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* Bit[13]- Enable PCIe port 13
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* Example:
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* port_enable = 0x14
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* Port 2 and 4 enabled for training/initialization
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*/
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#ifndef DEFAULT_PORT_ENABLE_MAP
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#define DEFAULT_PORT_ENABLE_MAP 0x0014
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#endif
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/**
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* Bitmap of ports that have slot or onboard device connected.
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* Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
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* #define DEFAULT_PORT_FORCE_GEN1 0x604
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*/
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#ifndef DEFAULT_PORT_FORCE_GEN1
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#define DEFAULT_PORT_FORCE_GEN1 0x0
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#endif
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/**
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* Bitmap of ports that have server hotplug support
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*/
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#ifndef DEFAULT_HOTPLUG_SUPPORT
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#define DEFAULT_HOTPLUG_SUPPORT 0x0
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#endif
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#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
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#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0}
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#endif
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#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
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#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000
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#endif
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/**
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* Default GPP1 core configuraton on NB #0/1/2/3.
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* 2 x8 slot, GFX_CONFIG_AABB
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* 1 x16 slot, GFX_CONFIG_AAAA
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*/
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#ifndef DEFAULT_GPP1_CONFIG
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#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB
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#endif
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/**
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* Default GPP2 core configuraton on NB #0/1/2/3.
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* 2 x8 slot, GFX_CONFIG_AABB
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* 1 x16 slot, GFX_CONFIG_AAAA
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*/
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#ifndef DEFAULT_GPP2_CONFIG
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#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB
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#endif
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/**
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* Default GPP3a core configuraton on NB #0/1/2/3.
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* 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1
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* 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2
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* 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3
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* 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4
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* 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5
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* 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6
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*/
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#ifndef DEFAULT_GPP3A_CONFIG
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#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111
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#endif
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/**
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* Default HT Transmitter de-emphasis setting
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*/
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#ifndef DEFAULT_HT_DEEMPASIES
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#define DEFAULT_HT_DEEMPASIES 0x3
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#endif
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/**
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* Default APIC nterrupt base for IOAPIC
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*/
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#ifndef DEFAULT_APIC_INTERRUPT_BASE
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#define DEFAULT_APIC_INTERRUPT_BASE 24
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#endif
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#define DEFAULT_PLATFORM_CONFIG(name) \
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NB_PLATFORM_CONFIG name = { \
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DEFAULT_PORT_ENABLE_MAP, \
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DEFAULT_PORT_FORCE_GEN1, \
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DEFAULT_HOTPLUG_SUPPORT, \
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DEFAULT_HOTPLUG_DESCRIPTOR, \
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DEFAULT_TEMPMMIO_BASE_ADDRESS, \
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DEFAULT_GPP1_CONFIG, \
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DEFAULT_GPP2_CONFIG, \
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DEFAULT_GPP3A_CONFIG, \
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DEFAULT_HT_DEEMPASIES, \
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/*DEFAULT_HT_PATH,*/ \
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DEFAULT_APIC_INTERRUPT_BASE, \
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}
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/**
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* Platform configuration
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*/
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typedef struct {
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UINT16 PortEnableMap; ///< Bitmap of enabled ports
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UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2
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UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug
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UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors
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UINT32 TemporaryMmio; ///< Temporary MMIO
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UINT32 Gpp1Config; ///< Default PCIe GFX core configuration
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UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration
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UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration
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UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level
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// HT_PATH NbHtPath; ///< HT path to NB
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UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC.
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} NB_PLATFORM_CONFIG;
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/**
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* Bridge CIMx configuration
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*/
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void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
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#endif //_RD890_CFG_H_
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