8ae8c88220
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
614 lines
20 KiB
C
614 lines
20 KiB
C
/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef H3FINIT_H
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#define H3FINIT_H
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/*----------------------------------------------------------------------------
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* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
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*
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*----------------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------------
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* DEFINITIONS AND MACROS
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*
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*-----------------------------------------------------------------------------
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*/
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/* Width equates for call backs */
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#define HT_WIDTH_8_BITS 8
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#define HT_WIDTH_16_BITS 16
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#define HT_WIDTH_4_BITS 4
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#define HT_WIDTH_2_BITS 2
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/* Frequency equates for call backs which take an actual frequency setting */
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#define HT_FREQUENCY_200M 0
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#define HT_FREQUENCY_400M 2
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#define HT_FREQUENCY_600M 4
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#define HT_FREQUENCY_800M 5
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#define HT_FREQUENCY_1000M 6
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#define HT_FREQUENCY_1200M 7
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#define HT_FREQUENCY_1400M 8
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#define HT_FREQUENCY_1600M 9
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#define HT_FREQUENCY_1800M 10
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#define HT_FREQUENCY_2000M 11
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#define HT_FREQUENCY_2200M 12
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#define HT_FREQUENCY_2400M 13
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#define HT_FREQUENCY_2600M 14
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/* Frequency Limit equates for call backs which take a frequency supported mask. */
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#define HT_FREQUENCY_LIMIT_200M 1
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#define HT_FREQUENCY_LIMIT_400M 7
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#define HT_FREQUENCY_LIMIT_600M 0x1F
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#define HT_FREQUENCY_LIMIT_800M 0x3F
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#define HT_FREQUENCY_LIMIT_1000M 0x7F
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#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F
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#define HT_FREQUENCY_LIMIT_1200M 0xFF
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#define HT_FREQUENCY_LIMIT_1400M 0x1FF
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#define HT_FREQUENCY_LIMIT_1600M 0x3FF
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#define HT_FREQUENCY_LIMIT_1800M 0x7FF
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#define HT_FREQUENCY_LIMIT_2000M 0xFFF
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#define HT_FREQUENCY_LIMIT_2200M 0x1FFF
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#define HT_FREQUENCY_LIMIT_2400M 0x3FFF
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#define HT_FREQUENCY_LIMIT_2600M 0x7FFF
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/*
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* Event Notify definitions
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*/
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/* Event Class definitions */
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#define HT_EVENT_CLASS_CRITICAL 1
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#define HT_EVENT_CLASS_ERROR 2
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#define HT_EVENT_CLASS_HW_FAULT 3
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#define HT_EVENT_CLASS_WARNING 4
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#define HT_EVENT_CLASS_INFO 5
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/* Event definitions. */
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/* Coherent subfunction events */
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#define HT_EVENT_COH_EVENTS 0x1000
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#define HT_EVENT_COH_NO_TOPOLOGY 0x1001
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#define HT_EVENT_COH_LINK_EXCEED 0x1002
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#define HT_EVENT_COH_FAMILY_FEUD 0x1003
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#define HT_EVENT_COH_NODE_DISCOVERED 0x1004
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#define HT_EVENT_COH_MPCAP_MISMATCH 0x1005
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/* Non-coherent subfunction events */
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#define HT_EVENT_NCOH_EVENTS 0x2000
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#define HT_EVENT_NCOH_BUID_EXCEED 0x2001
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#define HT_EVENT_NCOH_LINK_EXCEED 0x2002
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#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x2003
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#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x2004
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#define HT_EVENT_NCOH_DEVICE_FAILED 0x2005
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#define HT_EVENT_NCOH_AUTO_DEPTH 0x2006
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/* Optimization subfunction events */
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#define HT_EVENT_OPT_EVENTS 0x3000
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#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x3001
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#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x3002
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/* HW Fault events */
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#define HT_EVENT_HW_EVENTS 0x4000
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#define HT_EVENT_HW_SYNCHFLOOD 0x4001
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#define HT_EVENT_HW_HTCRC 0x4002
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/* The bbHT component (hb*) uses 0x5000 for events.
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* For consistency, we avoid that range here.
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*/
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/*----------------------------------------------------------------------------
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* TYPEDEFS, STRUCTURES, ENUMS
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*
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*----------------------------------------------------------------------------
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*/
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typedef struct {
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u8 **topolist;
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u8 AutoBusStart;
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/* Note: This should always be the form AutoBusCurrent+N*AutoBusIncrement, also bus 253-255 are reserved */
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u8 AutoBusMax;
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u8 AutoBusIncrement;
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/**----------------------------------------------------------------------------------------
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*
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* BOOL
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* AMD_CB_IgnoreLink(u8 Node, u8 Link)
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*
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* Description:
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* This routine is called every time a coherent link is found and then every
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* time a non-coherent link from a CPU is found.
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* Any coherent or non-coherent link from a CPU can be ignored and not used
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* for discovery or initialization. Useful for connection based systems.
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* (Note: not called for IO device to IO Device links.)
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*
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* Parameters:
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* @param[in] u8 node = The node on which this link is located
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* @param[in] u8 link = The link about to be initialized
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* @param[out] BOOL result = true to ignore this link and skip it
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* false to initialize the link normally
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*
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* ---------------------------------------------------------------------------------------
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*/
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BOOL (*AMD_CB_IgnoreLink)(u8 Node, u8 Link);
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/**----------------------------------------------------------------------------------------
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*
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* BOOL
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* AMD_CB_OverrideBusNumbers(u8 Node, u8 Link, u8 *SecBus, u8 *SubBus)
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*
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* Description:
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* This routine is called every time a non-coherent chain is processed.
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* If a system can not use the auto Bus numbering feature for non-coherent chain bus
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* assignments, this routine can provide explicit control. For each chain, provide
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* the bus number range to use.
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*
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* Parameters:
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* @param[in] u8 node = The node on which this chain is located
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* @param[in] u8 link = The link on the host for this chain
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* @param[out] u8 secBus = Secondary Bus number for this non-coherent chain
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* @param[out] u8* subBus = Subordinate Bus number
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* @param[out] BOOL result = true this routine is supplying the bus numbers
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* false use auto Bus numbering
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*
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* ---------------------------------------------------------------------------------------
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*/
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BOOL (*AMD_CB_OverrideBusNumbers)(u8 Node, u8 Link, u8 *SecBus, u8 *SubBus);
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/**----------------------------------------------------------------------------------------
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*
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* BOOL
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* AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
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*
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* Description:
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* This routine is called every time a non-coherent chain is processed.
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* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
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* swap list. The first part of the list controls the BUID assignment and the
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* second part of the list provides the device to device linking. Device orientation
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* can be detected automatically, or explicitly. See documentation for more details.
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*
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* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
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* based on each device's unit count.
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*
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* Parameters:
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* @param[in] u8 node = The node on which this chain is located
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* @param[in] u8 link = The link on the host for this chain
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* @param[out] u8** list = supply a pointer to a list
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* @param[out] BOOL result = true to use a manual list
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* false to initialize the link automatically
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*
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* ---------------------------------------------------------------------------------------
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*/
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BOOL (*AMD_CB_ManualBUIDSwapList)(u8 Node, u8 Link, u8 **List);
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/**----------------------------------------------------------------------------------------
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*
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* void
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* AMD_CB_DeviceCapOverride(u8 HostNode, u8 HostLink, u8 Depth, u8 Segment,
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* u8 Bus, u8 Dev, u32 DevVenID, u8 Link,
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* u8 *LinkWidthIn, u8 *LinkWidthOut, u16 *FreqCap)
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*
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* Description:
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* This routine is called once for every link on every IO device.
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* Update the width and frequency capability if needed for this device.
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* This is used along with device capabilities, the limit call backs, and northbridge
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* limits to compute the default settings. The components of the device's PCI config
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* address are provided, so its settings can be consulted if need be. The input width
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* and frequency are the reported device capabilities.
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*
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* Parameters:
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* @param[in] u8 hostNode = The node on which this chain is located
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* @param[in] u8 hostLink = The link on the host for this chain
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* @param[in] u8 Depth = The depth in the I/O chain from the Host
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* @param[in] u8 Segment = The Device's PCI Bus Segment number
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* @param[in] u8 Bus = The Device's PCI Bus number
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* @param[in] u8 Dev = The Device's PCI device Number
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* @param[in] u32 DevVenID = The Device's PCI Vendor + Device ID (offset 0x00)
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* @param[in] u8 Link = The Device's link number (0 or 1)
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* @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
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* @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
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* @param[in,out] u16* FreqCap = modify to change the link's frequency capability
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*
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* ---------------------------------------------------------------------------------------
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*/
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void (*AMD_CB_DeviceCapOverride)(
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u8 HostNode,
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u8 HostLink,
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u8 Depth,
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u8 Segment,
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u8 Bus,
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u8 Dev,
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u32 DevVenID,
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u8 Link,
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u8 *LinkWidthIn,
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u8 *LinkWidthOut,
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u16 *FreqCap
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);
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/**----------------------------------------------------------------------------------------
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*
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* void
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* AMD_CB_Cpu2CpuPCBLimits(u8 NodeA, u8 LinkA, u8 NodeB, u8 LinkB,
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* u8 *ABLinkWidthLimit, u8 *BALinkWidthLimit, u16 *PCBFreqCap)
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*
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* Description:
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* For each coherent connection this routine is called once.
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* Update the frequency and width if needed for this link (usually based on board
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* restriction). This is used with CPU device capabilities and northbridge limits
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* to compute the default settings. The input width and frequency are valid, but do
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* not necessarily reflect the minimum setting that will be chosen.
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*
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* Parameters:
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* @param[in] u8 nodeA = One node on which this link is located
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* @param[in] u8 linkA = The link on this node
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* @param[in] u8 nodeB = The other node on which this link is located
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* @param[in] u8 linkB = The link on that node
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* @param[in,out] u8* ABLinkWidthLimit = modify to change the Link Witdh In
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* @param[in,out] u8* BALinkWidthLimit = modify to change the Link Witdh Out
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* @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability
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*
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* ---------------------------------------------------------------------------------------
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*/
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void (*AMD_CB_Cpu2CpuPCBLimits)(
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u8 NodeA,
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u8 LinkA,
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u8 NodeB,
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u8 LinkB,
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u8 *ABLinkWidthLimit,
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u8 *BALinkWidthLimit,
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u16 *PCBFreqCap
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);
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/**----------------------------------------------------------------------------------------
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*
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* void
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* AMD_CB_IOPCBLimits(u8 HostNode, u8 HostLink, u8 Depth, u8 *DownstreamLinkWidthLimit,
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* u8 *UpstreamLinkWidthLimit, u16 *PCBFreqCap)
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*
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* Description:
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* For each non-coherent connection this routine is called once.
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* Update the frequency and width if needed for this link (usually based on board
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* restriction). This is used with device capabilities, device overrides, and northbridge limits
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* to compute the default settings. The input width and frequency are valid, but do
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* not necessarily reflect the minimum setting that will be chosen.
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*
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* Parameters:
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* @param[in] u8 hostNode = The node on which this link is located
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* @param[in] u8 hostLink = The link about to be initialized
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* @param[in] u8 Depth = The depth in the I/O chain from the Host
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* @param[in,out] u8* DownstreamLinkWidthLimit = modify to change the Link Witdh In
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* @param[in,out] u8* UpstreamLinkWidthLimit = modify to change the Link Witdh Out
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* @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability
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*
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* ---------------------------------------------------------------------------------------
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*/
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void (*AMD_CB_IOPCBLimits)(
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u8 HostNode,
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u8 HostLink,
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u8 Depth,
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u8 *DownstreamLinkWidthLimit,
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u8 *UpstreamLinkWidthLimit,
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u16 *PCBFreqCap
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);
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/**----------------------------------------------------------------------------------------
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*
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* BOOL
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* AMD_CB_SkipRegang(u8 NodeA, u8 LinkA, u8 NodeB, u8 LinkB)
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*
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* Description:
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* This routine is called whenever two sublinks are both connected to the same CPUs.
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* Normally, unganged subsinks between the same two CPUs are reganged.
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* Return true from this routine to leave the links unganged.
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*
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* Parameters:
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* @param[in] u8 nodeA = One node on which this link is located
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* @param[in] u8 linkA = The link on this node
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* @param[in] u8 nodeB = The other node on which this link is located
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* @param[in] u8 linkB = The link on that node
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* @param[out] BOOL result = true to leave link unganged
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* false to regang link automatically
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*
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* ---------------------------------------------------------------------------------------
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*/
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BOOL (*AMD_CB_SkipRegang)(
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u8 NodeA,
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u8 LinkA,
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u8 NodeB,
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u8 LinkB
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);
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/**----------------------------------------------------------------------------------------
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*
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* BOOL
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* AMD_CB_CustomizeTrafficDistribution()
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*
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* Description:
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* Near the end of HT initialization, this routine is called once.
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* If this routine will handle traffic distribution in a proprietary way,
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* after detecting which links to distribute traffic on and configuring the system,
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* return true. Return false to let the HT code detect and do traffic distribution
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* This routine can also be used to simply turn this feature off, or to pre-process
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* the system before normal traffic distribution.
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*
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* Parameters:
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* @param[out] BOOL result = true skip traffic distribution
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* false do normal traffic distribution
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*
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* ---------------------------------------------------------------------------------------
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*/
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BOOL (*AMD_CB_CustomizeTrafficDistribution)();
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/**----------------------------------------------------------------------------------------
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*
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* BOOL
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* AMD_CB_CustomizeBuffers(u8 Node)
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*
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* Description:
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* Near the end of HT initialization, this routine is called once per CPU node.
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* Implement proprietary buffer tuning and return true, or return false for normal tuning.
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* This routine can also be used to simply turn this feature off, or to pre-process
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* the system before normal tuning.
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*
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* Parameters:
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* @param[in] u8 node = buffer allocation may apply to this node
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* @param[out] BOOL result = true skip buffer allocation on this node
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* false tune buffers normally
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*
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* ---------------------------------------------------------------------------------------
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*/
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BOOL (*AMD_CB_CustomizeBuffers)( u8 node );
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/**----------------------------------------------------------------------------------------
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*
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* void
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* AMD_CB_OverrideDevicePort(u8 HostNode, u8 HostLink, u8 Depth, u8 *LinkWidthIn,
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* u8 *LinkWidthOut, u16 *LinkFrequency)
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*
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* Description:
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* Called once for each active link on each IO device.
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* Provides an opportunity to directly control the frequency and width,
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* intended for test and debug. The input frequency and width will be used
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* if not overridden.
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*
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* Parameters:
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* @param[in] u8 hostNode = The node on which this link is located
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* @param[in] u8 hostLink = The link about to be initialized
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* @param[in] u8 Depth = The depth in the I/O chain from the Host
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* @param[in] u8 Link = the link on the device (0 or 1)
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* @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
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* @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
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* @param[in,out] u16* LinkFrequency = modify to change the link's frequency capability
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*
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* ---------------------------------------------------------------------------------------
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*/
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void (*AMD_CB_OverrideDevicePort)(
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u8 HostNode,
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u8 HostLink,
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u8 Depth,
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u8 Link,
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u8 *LinkWidthIn,
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u8 *LinkWidthOut,
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u8 *LinkFrequency
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);
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/**----------------------------------------------------------------------------------------
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*
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* void
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* AMD_CB_OverrideCpuPort(u8 Node, u8 Link, u8 *LinkWidthIn, u8 *LinkWidthOut,
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* u16 *LinkFrequency)
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*
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* Description:
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* Called once for each active link on each CPU.
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* Provides an opportunity to directly control the frequency and width,
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* intended for test and debug. The input frequency and width will be used
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* if not overridden.
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*
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* Parameters:
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* @param[in] u8 node = One node on which this link is located
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* @param[in] u8 link = The link on this node
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* @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
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* @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
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* @param[in,out] u16* LinkFrequency = modify to change the link's frequency capability
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*
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*---------------------------------------------------------------------------------------
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*/
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void (*AMD_CB_OverrideCpuPort)(
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u8 Node,
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u8 Link,
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u8 *LinkWidthIn,
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u8 *LinkWidthOut,
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u8 *LinkFrequency
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);
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/**----------------------------------------------------------------------------------------
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*
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* void
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* AMD_CB_EventNotify(u8 evtClass, u16 event, const u8 *pEventData0)
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*
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* Description:
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* Errors, events, faults, warnings, and useful information are provided by
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* calling this routine as often as necessary, once for each notification.
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* See elsewhere in this file for class, event, and event data definitions.
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* See the documentation for more details.
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*
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* Parameters:
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* @param[in] u8 evtClass = What level event is this
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* @param[in] u16 event = A unique ID of this event
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* @param[in] u8* pEventData0 = useful data associated with the event.
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*
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* ---------------------------------------------------------------------------------------
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*/
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void (*AMD_CB_EventNotify) (
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u8 evtClass,
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u16 event,
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const u8 *pEventData0
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);
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} AMD_HTBLOCK;
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/*
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* Event Notification Structures
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* These structures are passed to AMD_CB_EventNotify as *pEventData0.
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*/
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/* For event HT_EVENT_HW_SYNCHFLOOD */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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} sHtEventHWSynchFlood;
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/* For event HT_EVENT_HW_HTCRC */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 laneMask;
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} sHtEventHWHtCrc;
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/* For event HT_EVENT_NCOH_BUS_MAX_EXCEED */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 bus;
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} sHTEventNcohBusMaxExceed;
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/* For event HT_EVENT_NCOH_LINK_EXCEED */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 depth;
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u8 maxLinks;
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} sHtEventNcohLinkExceed;
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/* For event HT_EVENT_NCOH_CFG_MAP_EXCEED */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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} sHtEventNcohCfgMapExceed;
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/* For event HT_EVENT_NCOH_BUID_EXCEED */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 depth;
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u8 currentBUID;
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u8 unitCount;
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} sHtEventNcohBuidExceed;
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/* For event HT_EVENT_NCOH_DEVICE_FAILED */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 depth;
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u8 attemptedBUID;
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} sHtEventNcohDeviceFailed;
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/* For event HT_EVENT_NCOH_AUTO_DEPTH */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 depth;
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} sHtEventNcohAutoDepth;
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/* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY,
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* HT_EVENT_OPT_REQUIRED_CAP_GEN3
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*/
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 depth;
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} sHtEventOptRequiredCap;
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/* For event HT_EVENT_COH_NO_TOPOLOGY */
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typedef struct
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{
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u8 eSize;
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u8 totalNodes;
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} sHtEventCohNoTopology;
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/* For event HT_EVENT_COH_LINK_EXCEED */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 targetNode;
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u8 totalNodes;
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u8 maxLinks;
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} sHtEventCohLinkExceed;
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/* For event HT_EVENT_COH_FAMILY_FEUD */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 totalNodes;
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} sHtEventCohFamilyFeud;
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/* For event HT_EVENT_COH_NODE_DISCOVERED */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 newNode;
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} sHtEventCohNodeDiscovered;
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/* For event HT_EVENT_COH_MPCAP_MISMATCH */
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typedef struct
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{
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u8 eSize;
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u8 node;
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u8 link;
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u8 sysMpCap;
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u8 totalNodes;
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} sHtEventCohMpCapMismatch;
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/*----------------------------------------------------------------------------
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* FUNCTIONS PROTOTYPE
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*
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*----------------------------------------------------------------------------
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*/
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void amdHtInitialize(AMD_HTBLOCK *pBlock);
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#endif /* H3FINIT_H */
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