c52d4f5745
- Add the doimage sources in util/marvell - Add dependency in root makefile - Add dependency in makefile for armada38x soc BUG=chrome-os-partner:47462 TEST=emerge-cyclone coreboot BRANCH=tot Change-Id: I81b30e0865cbd619a41659c3f2819ad3bafc5f24 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b2a990150580e0b879a346ed8b71b3765b66bab Original-Change-Id: I7e89b5e96206fde97ce69c296850122fd6c858f9 Original-Signed-off-by: Kefei Yao <kfyao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/318046 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
172 lines
5.3 KiB
C
172 lines
5.3 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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*******************************************************************************/
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#ifndef _INC_BOOTSTRAP__DEF_H
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#define _INC_BOOTSTRAP__DEF_H
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#include "bootstrap_os.h"
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#ifndef MV_ASMLANGUAGE
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#define MAIN_HDR_VERSION 1
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#define MAIN_HDR_NAND_SLC 0
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#define MAIN_HDR_NAND_MLC 1
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typedef struct BHR_t {
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/* type name byte order */
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MV_U8 blockID; /* 0 */
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MV_U8 flags; /* 1 */
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MV_U16 nandPageSize; /* 2-3 */
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MV_U32 blockSize; /* 4-7 */
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MV_U8 version; /* 8 */
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MV_U8 hdrSizeMsb; /* 9 */
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MV_U16 hdrSizeLsb; /* 10-11 */
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MV_U32 sourceAddr; /* 12-15 */
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MV_U32 destinationAddr; /* 16-19 */
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MV_U32 executionAddr; /* 20-23 */
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MV_U8 options; /* 24 */
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MV_U8 nandBlockSize; /* 25 */
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MV_U8 nandTechnology; /* 26 */
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MV_U8 rsvd4; /* 27 */
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MV_U16 rsvd2; /* 28-29 */
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MV_U8 ext; /* 30 */
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MV_U8 checkSum; /* 31 */
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} BHR_t, *pBHR_t;
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#define MAIN_HDR_GET_LEN(pHdr) \
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(((MV_U32)((pHdr)->hdrSizeMsb) << 16) | ((MV_U32)((pHdr)->hdrSizeLsb)))
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#define EXT_HDR_TYP_SECURITY 0x01
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#define EXT_HDR_TYP_BINARY 0x02
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#define EXT_HDR_TYP_REGISTER 0x03
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typedef struct headExtBHR_t {/* Common extension header head */
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// type name byte order
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MV_U8 type;
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MV_U8 lenMsb;
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MV_U16 lenLsb;
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} headExtBHR_t;
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#define EXT_HDR_SET_LEN(pHead, len) \
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do { \
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(pHead)->lenMsb = ((len)&0x00FF0000) >> 16; \
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(pHead)->lenLsb = (len)&0x0000FFFF; \
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} while (0)
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#define EXT_HDR_GET_LEN(pHead) \
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(((MV_U32)((pHead)->lenMsb) << 16) | ((pHead)->lenLsb))
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typedef struct tailExtBHR_t {/* Common extension header tail */
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// type name byte order
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MV_U8 nextHdr;
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MV_U8 delay;
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MV_U16 rsvd2;
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} tailExtBHR_t;
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typedef struct publicKey_t {/* public key*/
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MV_U8 Key[524];
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} publicKey_t;
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#define RSA_MAX_KEY_LEN_BYTES 256
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typedef struct secExtBHR_t {
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headExtBHR_t head;
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MV_U8 encrypt;
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MV_U8 rsrvd0;
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MV_U16 rsrvd1;
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publicKey_t pubKey;
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MV_U8 jtagEn;
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MV_U8 rsrvd2;
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MV_U16 rsrvd3;
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MV_U32 boxId;
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MV_U32 flashId;
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MV_U8 hdrSign[256];
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MV_U8 imgSign[256];
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publicKey_t cskArray[16];
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MV_U8 cskBlockSign[256];
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tailExtBHR_t tail;
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} secExtBHR_t, *pSecExtBHR_T;
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/***********************/
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/* SECURE PARAMS */
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/***********************/
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#define CSK_BLOCK_OFFSET 0x420
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#define PUB_KEY_SIZE 524
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#define CSK_KEY_NUM 16
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#define CSK_BLOCK_SIGN_OFFSET (CSK_BLOCK_OFFSET + (PUB_KEY_SIZE * CSK_KEY_NUM))
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/* 16 keys + 256 bytes long signature */
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#define CSK_BLOCK_SIZE ((PUB_KEY_SIZE * CSK_KEY_NUM) + 0x100)
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#define BOOTROM_SIZE (64 * 1024)
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#define EXT_HDR_BASE_SIZE (sizeof(headExtBHR_t) + sizeof(tailExtBHR_t))
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/* MAX size of entire headers block */
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#define MAX_HEADER_SIZE (192 * 1024)
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#define MAX_TWSI_HDR_SIZE \
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(60 * 1024) /* MAX eeprom is 64K & leave 4K for image and header */
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/* Boot Type - block ID */
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#define IBR_HDR_I2C_ID 0x4D
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#define IBR_HDR_SPI_ID 0x5A
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#define IBR_HDR_NAND_ID 0x8B
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#define IBR_HDR_SATA_ID 0x78
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#define IBR_HDR_PEX_ID 0x9C
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#define IBR_HDR_MMC_ID 0xAE
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#define IBR_HDR_UART_ID 0x69
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#define IBR_DEF_ATTRIB 0x00
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/* ROM flags */
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#define BHR_FLAG_PRINT_EN 0x01
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#define BHR_FLAG_RESERVED1 0x02
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#define BHR_FLAG_RESERVED2 0x04
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#define BHR_FLAG_RESERVED3 0x08
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#define BHR_FLAG_RESERVED4 0x10
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#define BHR_FLAG_RESERVED5 0x20
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#define BHR_FLAG_RESERVED6 0x40
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#define BHR_FLAG_RESERVED7 0x80
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/* ROM options */
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#define BHR_OPT_BAUDRATE_OFFS 0x0
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#define BHR_OPT_BAUDRATE_MASK (0x7 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_BAUD_DEFAULT (0x0 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_BAUD_2400 (0x1 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_BAUD_4800 (0x2 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_BAUD_9600 (0x3 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_BAUD_19200 (0x4 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_BAUD_38400 (0x5 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_BAUD_57600 (0x6 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_BAUD_115200 (0x7 << BHR_OPT_BAUDRATE_OFFS)
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#define BHR_OPT_UART_PORT_OFFS 0x3
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#define BHR_OPT_UART_PORT_MASK (0x3 << BHR_OPT_UART_PORT_OFFS)
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#define BHR_OPT_UART_MPPS_OFFS 0x5
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#define BHR_OPT_UART_MPPS_MASK (0x7 << BHR_OPT_UART_MPPS_OFFS)
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typedef struct _mvCpuArmClk {
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MV_U32 cpuClk; /* CPU clock MHz */
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MV_U32 ddrClk; /* DDR clock MHz */
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MV_U32 l2cClk; /* L2 cache clock MHz */
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} MV_CPU_ARM_CLK;
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#endif /* MV_ASMLANGUAGE */
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#endif /* _INC_BOOTSTRAP_H */
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