Aaron Durbin 8c8e2b7e4c arm64: remove secmon
It's been decided to only support ARM Trusted Firmware for
any EL3 monitor. That means any SoC that requires PSCI
needs to add its support for ATF otherwise multi-processor
bring up won't work.

Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11897
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07 03:28:06 +01:00

61 lines
1.5 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <console/uart.h>
#include <console/streams.h>
#include <device/pci.h>
#include <option.h>
#include <rules.h>
#include <version.h>
/* While in romstage, console loglevel is built-time constant. */
static ROMSTAGE_CONST int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
int console_log_level(int msg_level)
{
return (console_loglevel >= msg_level);
}
void console_init(void)
{
#if !defined(__PRE_RAM__)
console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
get_option(&console_loglevel, "debug_level");
#endif
#if CONFIG_EARLY_PCI_BRIDGE && !defined(__SMM__)
pci_early_bridge_init();
#endif
console_hw_init();
printk(BIOS_INFO, "\n\ncoreboot-%s%s %s %s starting...\n",
coreboot_version, coreboot_extra_version, coreboot_build,
#if ENV_BOOTBLOCK
"bootblock"
#elif ENV_ROMSTAGE
"romstage"
#elif ENV_RAMSTAGE
"ramstage"
#elif ENV_VERSTAGE
"verstage"
#else
"UNKNOWN"
#endif
);
}