8c9a89de99
APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
331 lines
8.7 KiB
C
331 lines
8.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <option.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include "chip.h"
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#include "i82801dx.h"
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#define NMI_OFF 0
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typedef struct southbridge_intel_i82801dx_config config_t;
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/**
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* Enable ACPI I/O range.
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*
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* @param dev PCI device with ACPI and PM BAR's
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*/
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static void i82801dx_enable_acpi(struct device *dev)
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{
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/* Set ACPI base address (I/O space). */
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pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
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/* Enable ACPI I/O range decode and ACPI power management. */
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pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
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}
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/**
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* Set miscellanous static southbridge features.
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*
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* @param dev PCI device with I/O APIC control registers
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*/
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static void i82801dx_enable_ioapic(struct device *dev)
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{
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u32 reg32;
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reg32 = pci_read_config32(dev, GEN_CNTL);
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reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
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reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
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reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
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reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
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pci_write_config32(dev, GEN_CNTL, reg32);
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printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
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set_ioapic_id(VIO_APIC_VADDR, 0x02);
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ioapic_set_boot_config(VIO_APIC_VADDR, true);
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}
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static void i82801dx_enable_serial_irqs(struct device *dev)
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{
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/* Set packet length and toggle silent mode bit. */
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
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}
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static void i82801dx_pirq_init(struct device *dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
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pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
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pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
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pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
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pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
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pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
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pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
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pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
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}
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static void i82801dx_power_options(struct device *dev)
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{
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u8 reg8;
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u16 reg16, pmbase;
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u32 reg32;
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const char *state;
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*
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* If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
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*/
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const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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reg8 &= 0xfe;
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switch (pwr_on) {
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case MAINBOARD_POWER_OFF:
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reg8 |= 1;
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state = "off";
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break;
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case MAINBOARD_POWER_ON:
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reg8 &= ~1;
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state = "on";
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break;
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case MAINBOARD_POWER_KEEP:
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reg8 &= ~1;
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state = "state keep";
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break;
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default:
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state = "undefined";
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}
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reg8 &= ~(1 << 3); /* minimum assertion is 1 to 2 RTCCLK */
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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printk(BIOS_INFO, "Set power %s after power failure.\n", state);
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/* Set up NMI on errors. */
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reg8 = inb(0x61);
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reg8 &= 0x0f; /* Higher Nibble must be 0 */
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reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
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// reg8 &= ~(1 << 2); /* PCI SERR# Enable */
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reg8 |= (1 << 2); /* PCI SERR# Disable for now */
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outb(reg8, 0x61);
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reg8 = inb(0x70);
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const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
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if (nmi_option) {
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printk(BIOS_INFO, "NMI sources enabled.\n");
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reg8 &= ~(1 << 7); /* Set NMI. */
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} else {
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printk(BIOS_INFO, "NMI sources disabled.\n");
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reg8 |= (1 << 7); /* Disable NMI. */
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}
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outb(reg8, 0x70);
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/* Set SMI# rate down and enable CPU_SLP# */
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 &= ~(3 << 0); // SMI# rate 1 minute
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reg16 |= (1 << 5); // CPUSLP_EN Desktop only
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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/* Set up power management block and determine sleep mode */
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reg32 = inl(pmbase + 0x04); // PM1_CNT
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reg32 &= ~(7 << 10); // SLP_TYP
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reg32 |= (1 << 0); // SCI_EN
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outl(reg32, pmbase + 0x04);
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}
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static void gpio_init(struct device *dev)
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{
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/* This should be done in romstage.c already */
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pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL, 0x10);
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}
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static void i82801dx_rtc_init(struct device *dev)
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{
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u8 reg8;
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u32 reg32;
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int rtc_failed;
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~(1 << 1); /* Preserve the power fail state. */
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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}
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reg32 = pci_read_config32(dev, GEN_STS);
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rtc_failed |= reg32 & (1 << 2);
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cmos_init(rtc_failed);
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/* Enable access to the upper 128 byte bank of CMOS RAM. */
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pci_write_config8(dev, RTC_CONF, 0x04);
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}
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static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
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{
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u16 reg16;
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int i;
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reg16 = pci_read_config16(dev, PCI_DMA_CFG);
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reg16 &= 0x300;
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for (i = 0; i < 8; i++) {
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if (i == 4)
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continue;
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reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
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}
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pci_write_config16(dev, PCI_DMA_CFG, reg16);
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}
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static void i82801dx_lpc_decode_en(struct device *dev)
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{
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/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
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* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
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* Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
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* We also need to set the value for LPC I/F Enables Register.
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*/
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pci_write_config8(dev, COM_DEC, 0x10);
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pci_write_config16(dev, LPC_EN, 0x300F);
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}
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/* ICH4 does not mention HPET in the docs, but
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* all ICH3 and ICH4 do have HPETs built in.
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*/
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static void enable_hpet(struct device *dev)
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{
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u32 reg32, hpet, val;
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/* Set HPET base address and enable it */
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printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS);
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reg32 = pci_read_config32(dev, GEN_CNTL);
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/*
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* Bit 17 is HPET enable bit.
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* Bit 16:15 control the HPET base address.
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*/
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reg32 &= ~(3 << 15); /* Clear it */
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hpet = CONFIG_HPET_ADDRESS >> 12;
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hpet &= 0x3;
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reg32 |= (hpet << 15);
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reg32 |= (1 << 17); /* Enable HPET. */
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pci_write_config32(dev, GEN_CNTL, reg32);
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/* Check to see whether it took */
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reg32 = pci_read_config32(dev, GEN_CNTL);
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val = reg32 >> 15;
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val &= 0x7;
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if ((val & 0x4) && (hpet == (val & 0x3))) {
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printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS);
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} else {
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printk(BIOS_WARNING, "HPET was not enabled correctly\n");
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reg32 &= ~(1 << 17); /* Clear Enable */
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pci_write_config32(dev, GEN_CNTL, reg32);
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}
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}
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static void lpc_init(struct device *dev)
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{
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i82801dx_enable_acpi(dev);
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/* IO APIC initialization. */
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i82801dx_enable_ioapic(dev);
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i82801dx_enable_serial_irqs(dev);
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/* Setup the PIRQ. */
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i82801dx_pirq_init(dev);
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/* Setup power options. */
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i82801dx_power_options(dev);
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/* Set the state of the GPIO lines. */
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gpio_init(dev);
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/* Initialize the real time clock. */
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i82801dx_rtc_init(dev);
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/* Route DMA. */
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i82801dx_lpc_route_dma(dev, 0xff);
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/* Initialize ISA DMA. */
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isa_dma_init();
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/* Setup decode ports and LPC I/F enables. */
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i82801dx_lpc_decode_en(dev);
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/* Initialize the High Precision Event Timers */
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enable_hpet(dev);
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/* Don't allow evil boot loaders, kernels, or
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* userspace applications to deceive us:
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*/
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if (CONFIG(HAVE_SMI_HANDLER) && !CONFIG(PARALLEL_MP))
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aseg_smm_lock();
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}
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static void i82801dx_lpc_read_resources(struct device *dev)
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{
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struct resource *res;
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add an extra subtractive resource for both memory and I/O. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->base = 0;
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res->size = 0x1000;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->base = 0xff800000;
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res->size = 0x00800000; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 3); /* IOAPIC */
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res->base = IO_APIC_ADDR;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static struct device_operations lpc_ops = {
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.read_resources = i82801dx_lpc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = lpc_init,
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.scan_bus = scan_static_bus,
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.enable = i82801dx_enable,
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};
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/* 82801DB/DBL */
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static const struct pci_driver lpc_driver_db __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
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};
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/* 82801DBM */
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static const struct pci_driver lpc_driver_dbm __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,
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};
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