8ca8d7665d
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
357 lines
10 KiB
C
357 lines
10 KiB
C
/*
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* intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
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*
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* Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
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*
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* Copyright 2000 Silicon Integrated System Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
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*
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* $Id$
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*/
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#ifndef lint
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static char rcsid[] = "$Id$";
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#endif
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#include <console/console.h>
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#include <mem.h>
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#include <cpu/p6/msr.h>
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#include <cpu/p6/mtrr.h>
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#include <cpu/k7/mtrr.h>
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#define arraysize(x) (sizeof(x)/sizeof((x)[0]))
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static unsigned int mtrr_msr[] = {
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MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
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MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
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MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
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};
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static void intel_enable_fixed_mtrr(void)
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{
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unsigned long low, high;
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rdmsr(MTRRdefType_MSR, low, high);
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low |= 0xc00;
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wrmsr(MTRRdefType_MSR, low, high);
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}
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static void intel_enable_var_mtrr(void)
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{
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unsigned long low, high;
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rdmsr(MTRRdefType_MSR, low, high);
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low |= 0x800;
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wrmsr(MTRRdefType_MSR, low, high);
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}
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static inline void disable_cache(void)
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{
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unsigned int tmp;
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/* Disable cache */
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/* Write back the cache and flush TLB */
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asm volatile (
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"movl %%cr0, %0\n\t"
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"orl $0x40000000, %0\n\t"
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"wbinvd\n\t"
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"movl %0, %%cr0\n\t"
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"wbinvd\n\t"
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:"=r" (tmp)
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::"memory");
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}
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static inline void enable_cache(void)
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{
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unsigned int tmp;
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// turn cache back on.
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asm volatile (
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"movl %%cr0, %0\n\t"
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"andl $0x9fffffff, %0\n\t"
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"movl %0, %%cr0\n\t"
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:"=r" (tmp)
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::"memory");
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}
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/* setting variable mtrr, comes from linux kernel source */
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static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
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{
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unsigned long base_high, base_low;
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unsigned long mask_high, mask_low;
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base_high = basek >> 22;
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base_low = basek << 10;
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if (sizek < 4*1024*1024) {
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mask_high = 0x0F;
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mask_low = ~((sizek << 10) -1);
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}
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else {
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mask_high = 0x0F & (~((sizek >> 22) -1));
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mask_low = 0;
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}
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if (reg >= 8)
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return;
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// it is recommended that we disable and enable cache when we
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// do this.
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disable_cache();
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if (sizek == 0) {
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/* The invalid bit is kept in the mask, so we simply clear the
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relevant mask register to disable a range. */
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wrmsr (MTRRphysMask_MSR (reg), 0, 0);
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} else {
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/* Bit 32-35 of MTRRphysMask should be set to 1 */
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wrmsr (MTRRphysBase_MSR(reg), base_low | type, base_high);
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wrmsr (MTRRphysMask_MSR(reg), mask_low | 0x800, mask_high);
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}
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enable_cache();
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}
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/* setting variable mtrr, comes from linux kernel source */
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void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
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{
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unsigned int tmp;
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if (reg >= 8)
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return;
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// it is recommended that we disable and enable cache when we
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// do this.
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disable_cache();
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if (size == 0) {
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/* The invalid bit is kept in the mask, so we simply clear the
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relevant mask register to disable a range. */
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wrmsr (MTRRphysMask_MSR (reg), 0, 0);
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} else {
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/* Bit 32-35 of MTRRphysMask should be set to 1 */
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wrmsr (MTRRphysBase_MSR (reg), base | type, 0);
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wrmsr (MTRRphysMask_MSR (reg), ~(size - 1) | 0x800, 0x0F);
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}
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// turn cache back on.
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enable_cache();
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}
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/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
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static inline unsigned int fms(unsigned int x)
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{
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int r;
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__asm__("bsrl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $0,%0\n"
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"1:" : "=r" (r) : "g" (x));
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return r;
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}
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/* fms: find least sigificant bit set */
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static inline unsigned int fls(unsigned int x)
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{
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int r;
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__asm__("bsfl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $32,%0\n"
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"1:" : "=r" (r) : "g" (x));
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return r;
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}
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/* setting up variable and fixed mtrr
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*
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* From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
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* 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
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* 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
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* requirement. So a 8K range must be 8K aligned not 4K aligned.
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*
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* These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
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* For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
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* A 124MB (128MB - 4MB SMA) example:
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* ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
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* But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
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*
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* In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
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* If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
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* whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
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* The same 124MB example:
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* ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
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* or a 156MB (128MB + 32MB - 4MB SMA) example:
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* ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
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*/
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/* 2 MTRRS are reserved for the operating system */
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#define BIOS_MTRRS 6
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#define OS_MTRRS 2
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#define MTRRS (BIOS_MTRRS + OS_MTRRS)
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static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
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{
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unsigned int i;
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unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
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unsigned long low, high;
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low = high = 0; /* Shut up gcc */
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for(i = first; i < last; i++) {
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/* When I switch to a new msr read it in */
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if (fixed_msr != i >> 3) {
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/* But first write out the old msr */
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if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
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disable_cache();
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wrmsr(mtrr_msr[fixed_msr], low, high);
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enable_cache();
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}
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fixed_msr = i>>3;
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rdmsr(mtrr_msr[fixed_msr], low, high);
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}
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if ((i & 7) < 4) {
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low &= ~(0xff << ((i&3)*8));
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low |= type << ((i&3)*8);
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} else {
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high &= ~(0xff << ((i&3)*8));
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high |= type << ((i&3)*8);
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}
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}
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/* Write out the final msr */
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if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
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disable_cache();
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wrmsr(mtrr_msr[fixed_msr], low, high);
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enable_cache();
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}
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}
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static unsigned fixed_mtrr_index(unsigned long addrk)
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{
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unsigned index;
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index = (addrk - 0) >> 6;
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if (index >= 8) {
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index = ((addrk - 8*64) >> 4) + 8;
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}
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if (index >= 24) {
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index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
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}
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if (index > NUM_FIXED_RANGES) {
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index = NUM_FIXED_RANGES;
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}
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return index;
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}
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static unsigned int range_to_mtrr(unsigned int reg,
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unsigned long range_startk, unsigned long range_sizek,
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unsigned long next_range_startk)
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{
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if (!range_sizek || (reg >= BIOS_MTRRS)) {
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return reg;
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}
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while(range_sizek) {
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unsigned long max_align, align;
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unsigned long sizek;
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/* Compute the maximum size I can make a range */
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max_align = fls(range_startk);
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align = fms(range_sizek);
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if (align > max_align) {
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align = max_align;
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}
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sizek = 1 << align;
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printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type WB\n",
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reg, range_startk >>10, sizek >> 10);
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intel_set_var_mtrr(reg++, range_startk, sizek, MTRR_TYPE_WRBACK);
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range_startk += sizek;
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range_sizek -= sizek;
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if (reg >= BIOS_MTRRS)
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break;
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}
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return reg;
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}
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void setup_mtrrs(struct mem_range *mem)
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{
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/* Try this the simple way of incrementally adding together
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* mtrrs. If this doesn't work out we can get smart again
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* and clear out the mtrrs.
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*/
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struct mem_range *memp;
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unsigned long range_startk, range_sizek;
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unsigned int reg;
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printk_debug("\n");
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/* Initialized the fixed_mtrrs to uncached */
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printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
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0, NUM_FIXED_RANGES);
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set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHABLE);
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/* Now see which of the fixed mtrrs cover ram.
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*/
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for(memp = mem; memp->sizek; memp++) {
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unsigned int start_mtrr;
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unsigned int last_mtrr;
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start_mtrr = fixed_mtrr_index(memp->basek);
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last_mtrr = fixed_mtrr_index(memp->basek + memp->sizek);
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if (start_mtrr >= NUM_FIXED_RANGES) {
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break;
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}
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printk_debug("Setting fixed MTRRs(%d-%d) type: WB\n",
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start_mtrr, last_mtrr);
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set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
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}
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printk_debug("DONE fixed MTRRs\n");
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/* Cache as many memory areas as possible */
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/* FIXME is there an algorithm for computing the optimal set of mtrrs?
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* In some cases it is definitely possible to do better.
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*/
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range_startk = 0;
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range_sizek = 0;
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reg = 0;
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for (memp = mem; memp->sizek; memp++) {
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/* See if I can merge with the last range
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* Either I am below 1M and the fixed mtrrs handle it, or
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* the ranges touch.
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*/
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if ((memp->basek <= 1024) || (range_startk + range_sizek == memp->basek)) {
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unsigned long endk = memp->basek + memp->sizek;
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range_sizek = endk - range_startk;
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continue;
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}
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/* Write the range mtrrs */
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if (range_sizek != 0) {
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reg = range_to_mtrr(reg, range_startk, range_sizek, memp->basek);
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range_startk = 0;
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range_sizek = 0;
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if (reg >= BIOS_MTRRS)
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break;
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}
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/* Allocate an msr */
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range_startk = memp->basek;
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range_sizek = memp->sizek;
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}
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/* Write the last range */
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reg = range_to_mtrr(reg, range_startk, range_sizek, 0);
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printk_debug("DONE variable MTRRs\n");
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printk_debug("Clear out the extra MTRR's\n");
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/* Clear out the extra MTRR's */
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while(reg < MTRRS) {
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intel_set_var_mtrr(reg++, 0, 0, 0);
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}
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/* enable fixed MTRR */
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printk_debug("call intel_enable_fixed_mtrr()\n");
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intel_enable_fixed_mtrr();
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printk_debug("call intel_enable_var_mtrr()\n");
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intel_enable_var_mtrr();
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printk_debug("Leave %s\n", __FUNCTION__);
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}
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