8cbd569f74
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018-present Facebook, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/exception.h>
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#include <console/console.h>
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#include <delay.h>
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#include <program_loading.h>
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#include <symbols.h>
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#include <timestamp.h>
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#include <soc/bootblock.h>
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DECLARE_OPTIONAL_REGION(timestamp);
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__attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ }
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__attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ }
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__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ }
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__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ }
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/* C code entry point for the boot block */
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void bootblock_main(const uint64_t reg_x0,
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const uint64_t reg_x1,
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const uint64_t reg_pc)
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{
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uint64_t base_timestamp = 0;
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init_timer();
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if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS))
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base_timestamp = timestamp_get();
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/* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */
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if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)
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timestamp_init(base_timestamp);
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bootblock_soc_early_init();
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bootblock_mainboard_early_init();
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if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
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console_init();
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exception_init();
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if (reg_x0)
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printk(BIOS_ERR,
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"BOOTBLOCK: RST Boot Failure Code %lld\n",
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reg_x0);
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printk(BIOS_DEBUG, "BOOTBLOCK: FDT 0x%llX\n", reg_x1);
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}
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bootblock_soc_init();
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bootblock_mainboard_init();
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run_romstage();
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}
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