8cc8468971
And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
96 lines
2.2 KiB
C
96 lines
2.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <delay.h>
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#include <stdint.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/speedstep.h>
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/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
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static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
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{
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tsc->lo = (a & 0xffff) * (b & 0xffff);
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tsc->hi = ((tsc->lo >> 16)
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+ ((a & 0xffff) * (b >> 16))
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+ ((b & 0xffff) * (a >> 16)));
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tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
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tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
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}
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/**
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* Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
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*/
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void udelay(u32 us)
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{
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u32 dword;
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tsc_t tsc, tsc1, tscd;
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msr_t msr;
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u32 fsb = 0, divisor;
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u32 d; /* ticks per us */
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msr = rdmsr(MSR_FSB_FREQ);
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switch (msr.lo & 0x07) {
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case 5:
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fsb = 400;
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break;
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case 1:
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fsb = 533;
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break;
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case 3:
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fsb = 667;
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break;
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case 2:
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fsb = 800;
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break;
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case 0:
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fsb = 1067;
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break;
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case 4:
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fsb = 1333;
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break;
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case 6:
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fsb = 1600;
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break;
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}
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msr = rdmsr(0x198);
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divisor = (msr.hi >> 8) & 0x1f;
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d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */
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multiply_to_tsc(&tscd, us, d);
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tsc1 = rdtsc();
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dword = tsc1.lo + tscd.lo;
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if ((dword < tsc1.lo) || (dword < tscd.lo)) {
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tsc1.hi++;
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}
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tsc1.lo = dword;
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tsc1.hi += tscd.hi;
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do {
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tsc = rdtsc();
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} while ((tsc.hi < tsc1.hi)
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|| ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
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}
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