d385ed29b9
process. The PPC support is still stubbed, with commented out x86 code as guide line for an implementor. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
124 lines
4.7 KiB
C
124 lines
4.7 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARCH_IO_H
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#define _ARCH_IO_H
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extern uint32_t isa_io_base;
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#define readb(_a) (*(volatile unsigned char *) (_a))
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#define readw(_a) (*(volatile unsigned short *) (_a))
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#define readl(_a) (*(volatile unsigned long *) (_a))
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#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v))
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#define writew(_v, _a) (*(volatile unsigned short *) (_a) = (_v))
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#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v))
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static inline unsigned long inl(int port)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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unsigned long val;
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__asm__ __volatile__("lhbrx %0,0,%1; eieio":"=r"(val):
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"r"(addr), "m"(*addr));
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return val;
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}
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static inline unsigned short inw(int port)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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unsigned short val;
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__asm__ __volatile__("lwbrx %0,0,%1; eieio":"=r"(val):"r"(addr), "m"(*addr));
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return val;
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}
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static inline unsigned char inb(int port)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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unsigned char val;
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__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(val):"m"(*addr));
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return val;
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}
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static inline void outl(unsigned long val, int port)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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__asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
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}
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static inline void outw(unsigned short val, int port)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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__asm__ __volatile__("sthbrx %1,0,%2; eieio":"=m"(*addr):"r"(val),"r"(addr));
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}
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static inline void outb(unsigned char val, int port)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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__asm__ __volatile__("stwbrx %1,0,%2; eieio":"=m"(*addr):"r"(val), "r"(addr));
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}
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static inline void outsl(int port, const void *addr, unsigned long count)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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//__asm__ __volatile__("rep; outsl" : "+S"(addr), "+c"(count) : "d"(port));
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}
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static inline void outsw(int port, const void *addr, unsigned long count)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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//__asm__ __volatile__("rep; outsw" : "+S"(addr), "+c"(count) : "d"(port));
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}
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static inline void outsb(int port, const void *addr, unsigned long count)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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//__asm__ __volatile__("rep; outsb" : "+S"(addr), "+c"(count) : "d"(port));
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}
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static inline void insl(int port, void *addr, unsigned long count)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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//__asm__ __volatile__("rep; insl" : "+D"(addr), "+c"(count) : "d"(port));
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}
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static inline void insw(int port, void *addr, unsigned long count)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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//__asm__ __volatile__("rep; insw" : "+D"(addr), "+c"(count) : "d"(port));
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}
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static inline void insb(int port, void *addr, unsigned long count)
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{
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volatile unsigned char *addr = (volatile unsigned char *)(isa_io_base + port);
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//__asm__ __volatile__("rep; insb" : "+D"(addr), "+c"(count) : "d"(port));
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}
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#endif
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