8e9906c19a
Change-Id: I8fa26e7a398eee855c31a76f0f89b4111368c2a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
146 lines
3.9 KiB
Plaintext
146 lines
3.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config NORTHBRIDGE_INTEL_HASWELL
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bool
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select CPU_INTEL_HASWELL
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select CACHE_MRC_SETTINGS
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select INTEL_DDI
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select INTEL_GMA_ACPI
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select USE_DDR3
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if NORTHBRIDGE_INTEL_HASWELL
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config USE_NATIVE_RAMINIT
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bool "[NOT WORKING] Use native raminit"
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default n
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select HAVE_DEBUG_RAM_SETUP
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help
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Select if you want to use coreboot implementation of raminit rather than
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MRC.bin. Currently incomplete and does not boot.
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config HASWELL_VBOOT_IN_BOOTBLOCK
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depends on VBOOT
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bool "Start verstage in bootblock"
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default y
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select VBOOT_STARTS_IN_BOOTBLOCK
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help
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Haswell can either start verstage in a separate stage
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right after the bootblock has run or it can start it
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after romstage for compatibility reasons.
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Haswell however uses a mrc.bin to initialize memory which
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needs to be located at a fixed offset. Therefore even with
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a separate verstage starting after the bootblock that same
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binary is used meaning a jump is made from RW to the RO region
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and back to the RW region after the binary is done.
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config USE_BROADWELL_MRC
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bool "Use Broadwell MRC.bin"
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depends on !USE_NATIVE_RAMINIT
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help
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Haswell MRC.bin has several limitations: it does not support
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Broadwell CPUs nor 9-series PCHs, it does not initialise PEG
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ports properly and it can't use more than one SPD file entry
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at the same time (which would be useful for memory overclock
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when using different DIMMs, without patching SPD EEPROMs). A
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workaround for some of these limitations is to use Broadwell
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MRC.bin instead.
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config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK
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config VGA_BIOS_ID
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string
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default "8086,0166"
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config ECAM_MMCONF_BASE_ADDRESS
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default 0xf0000000
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config ECAM_MMCONF_BUS_NUMBER
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int
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default 64
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config DCACHE_RAM_BASE
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hex
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default 0xff7c0000
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config DCACHE_RAM_SIZE
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hex
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default 0x40000 if USE_NATIVE_RAMINIT
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default 0x10000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x0 if USE_NATIVE_RAMINIT
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default 0x30000
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help
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The amount of cache-as-ram region required by the reference code.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x20000 if USE_NATIVE_RAMINIT
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default 0x2000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config HAVE_MRC
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bool "Add a System Agent binary"
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depends on !USE_NATIVE_RAMINIT
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help
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Select this option to add a System Agent binary to
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the resulting coreboot image.
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Note: Without this binary coreboot will not work
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config MRC_FILE
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string "Intel System Agent path and filename"
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depends on HAVE_MRC
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default "mrc.bin"
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help
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The path and filename of the file to use as System Agent
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binary.
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config HASWELL_HIDE_PEG_FROM_MRC
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bool "Hide PEG devices from MRC to work around hardcoded MRC behavior"
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depends on !USE_NATIVE_RAMINIT
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default y
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help
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If set, hides all PEG devices from MRC. This allows the iGPU
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to be used even when a dedicated graphics card is present.
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However, it prevents MRC from programming PEG AFE registers,
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which can make PEG devices unstable. When unsure, choose N.
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# The UEFI System Agent binary needs to be at a fixed offset in the flash
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# and can therefore only reside in the COREBOOT fmap region
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config RO_REGION_ONLY
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string
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depends on VBOOT
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default "mrc.bin"
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config INTEL_GMA_BCLV_OFFSET
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default 0x48254
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config ENABLE_DDR_2X_REFRESH
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bool "Enable DRAM Refresh 2x support"
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default n
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help
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When enabled, the memory controller will refresh the DRAM twice as often.
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This probably only happens when the DRAM gets hot, but what MRC exactly
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does when this setting is enabled has not been investigated.
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config FIXED_MCHBAR_MMIO_BASE
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default 0xfed10000
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config FIXED_DMIBAR_MMIO_BASE
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default 0xfed18000
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config FIXED_EPBAR_MMIO_BASE
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default 0xfed19000
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endif
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