8f09688d23
Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34738 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <cbmem.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/systemagent.h>
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#include <soc/smm.h>
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#include <stdint.h>
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static uintptr_t dpr_region_start(void)
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{
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/*
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* Base of DPR is top of usable DRAM below 4GiB. The register has
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* 1 MiB alignment and reports the TOP of the range, the base
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* must be calculated from the size in MiB in bits 11:4.
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*/
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uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR);
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uintptr_t tom = dpr & ~((1 << 20) - 1);
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/* Subtract DMA Protected Range size if enabled */
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if (dpr & DPR_EPM)
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tom -= (dpr & DPR_SIZE_MASK) << 16;
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return tom;
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}
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void *cbmem_top(void)
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{
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return (void *) dpr_region_start();
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
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uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM);
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tseg = ALIGN_DOWN(tseg, 1 * MiB);
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bgsm = ALIGN_DOWN(bgsm, 1 * MiB);
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*start = tseg;
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*size = bgsm - tseg;
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}
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