8f89549d3c
This patch adds support for Intel Xeon-SP. This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base. The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
60 lines
1.8 KiB
Makefile
60 lines
1.8 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2019 - 2020 Intel Corporation
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## Copyright (C) 2019 - 2020 Facebook Inc
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y)
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
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bootblock-y += bootblock/bootblock.c
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bootblock-y += spi.c
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postcar-y += soc_util.c
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postcar-y += spi.c
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romstage-y += soc_util.c
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romstage-y += reset.c
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romstage-y += romstage.c
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romstage-y += soc_util.c
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romstage-y += spi.c
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romstage-y += hob_display.c
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romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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ramstage-y += soc_util.c
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ramstage-y += uncore.c
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ramstage-y += reset.c
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ramstage-y += chip.c
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ramstage-y += soc_util.c
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ramstage-y += lpc.c
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ramstage-y += cpu.c
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ramstage-y += spi.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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ramstage-y += hob_display.c
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CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
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CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
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endif ## CONFIG_SOC_INTEL_XEON_SP
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