8fc5c64403
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the
southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact
same ASL code though. So share this in the directory
`src/southbridge/intel/common/acpi`.
Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
55 lines
1.4 KiB
Plaintext
55 lines
1.4 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0
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"COREv2", // OEM id
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"COREBOOT", // OEM table id
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0x20090419 // OEM revision
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)
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{
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// Some generic macros
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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// General Purpose Events
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//#include "acpi/gpe.asl"
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//#include "acpi/thermal.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/i945/acpi/i945.asl>
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#include <southbridge/intel/i82801gx/acpi/ich7.asl>
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}
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}
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/* Chipset specific sleep states */
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#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
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}
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