8ffd050cf0
Change-Id: Ic8ffd26e61c0c3f27872699bb6aa9c39204155b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16390 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
67 lines
1.3 KiB
C
67 lines
1.3 KiB
C
#ifndef CPU_X86_TSC_H
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#define CPU_X86_TSC_H
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#include <stdint.h>
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#if CONFIG_TSC_SYNC_MFENCE
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#define TSC_SYNC "mfence\n"
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#elif CONFIG_TSC_SYNC_LFENCE
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#define TSC_SYNC "lfence\n"
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#else
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#define TSC_SYNC
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#endif
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struct tsc_struct {
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unsigned lo;
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unsigned hi;
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};
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typedef struct tsc_struct tsc_t;
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static inline tsc_t rdtsc(void)
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{
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tsc_t res;
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asm volatile (
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TSC_SYNC
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"rdtsc"
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: "=a" (res.lo), "=d"(res.hi) /* outputs */
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);
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return res;
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}
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#if !defined(__ROMCC__)
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/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.
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* This code is used to prevent use of libgcc's umoddi3.
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*/
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static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
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{
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tsc->lo = (a & 0xffff) * (b & 0xffff);
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tsc->hi = ((tsc->lo >> 16)
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+ ((a & 0xffff) * (b >> 16))
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+ ((b & 0xffff) * (a >> 16)));
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tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
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tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
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}
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/* Too many registers for ROMCC */
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static inline unsigned long long rdtscll(void)
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{
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unsigned long long val;
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asm volatile (
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TSC_SYNC
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"rdtsc"
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: "=A" (val)
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);
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return val;
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}
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static inline uint64_t tsc_to_uint64(tsc_t tstamp)
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{
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return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
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}
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#endif
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/* Provided by CPU/chipset code for the TSC rate in MHz. */
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unsigned long tsc_freq_mhz(void);
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#endif /* CPU_X86_TSC_H */
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