120aec0902
We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
114 lines
3.3 KiB
C
114 lines
3.3 KiB
C
/*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <libpayload.h>
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#include <stdint.h>
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struct mmio32_uart {
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union {
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uint32_t thr; // Transmit holding register.
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uint32_t rbr; // Receive buffer register.
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uint32_t dll; // Divisor latch lsb.
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};
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union {
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uint32_t ier; // Interrupt enable register.
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uint32_t dlm; // Divisor latch msb.
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};
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union {
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uint32_t iir; // Interrupt identification register.
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uint32_t fcr; // FIFO control register.
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};
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uint32_t lcr; // Line control register.
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uint32_t mcr; // Modem control register.
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uint32_t lsr; // Line status register.
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uint32_t msr; // Modem status register.
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} __attribute__ ((packed));
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enum {
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LSR_DR = 0x1 << 0, // Data ready.
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LSR_OE = 0x1 << 1, // Overrun.
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LSR_PE = 0x1 << 2, // Parity error.
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LSR_FE = 0x1 << 3, // Framing error.
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LSR_BI = 0x1 << 4, // Break.
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LSR_THRE = 0x1 << 5, // Xmit holding register empty.
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LSR_TEMT = 0x1 << 6, // Xmitter empty.
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LSR_ERR = 0x1 << 7 // Error.
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};
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static struct mmio32_uart *uart = NULL;
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void serial_putchar(unsigned int c)
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{
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while (!(readl(&uart->lsr) & LSR_THRE))
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/* wait for transmit register to clear */;
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writel((char)c, &uart->thr);
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if (c == '\n')
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serial_putchar('\r');
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}
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int serial_havechar(void)
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{
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uint8_t lsr = readl(&uart->lsr);
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return (lsr & LSR_DR) == LSR_DR;
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}
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int serial_getchar(void)
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{
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while (!serial_havechar())
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/* wait for character */;
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return readl(&uart->rbr);
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}
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static struct console_output_driver mmio32_serial_output = {
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.putchar = &serial_putchar
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};
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static struct console_input_driver mmio32_serial_input = {
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.havekey = &serial_havechar,
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.getchar = &serial_getchar
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};
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void serial_init(void)
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{
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if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr)
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return;
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uart = (struct mmio32_uart *)(uintptr_t)lib_sysinfo.serial->baseaddr;
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}
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void serial_console_init(void)
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{
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serial_init();
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if (uart) {
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console_add_output_driver(&mmio32_serial_output);
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console_add_input_driver(&mmio32_serial_input);
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}
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}
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