90e63deeba
Follow-up on commitsa5d72a3and53052fefor f12 and f15. OEM Hooks are not BiosCallOuts. Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14888 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
111 lines
3.2 KiB
C
111 lines
3.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include "Ids.h"
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#include "heapManager.h"
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#include "SB700.h"
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#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
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#include <stdlib.h>
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#include <southbridge/amd/cimx/sb700/smbus_spd.h>
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#ifdef __PRE_RAM__
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/* This define is used when selecting the appropriate socket for the SPD read
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* because this is a multi-socket design.
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*/
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#define LTC4305_SMBUS_ADDR (0x94)
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static void select_socket(UINT8 socket_id)
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{
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AMD_CONFIG_PARAMS StdHeader;
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UINT32 PciData32;
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UINT8 PciData8;
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PCI_ADDR PciAddress;
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/* Set SMBus MMIO. */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
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PciData32 = (SMBUS0_BASE_ADDRESS & 0xFFFFFFF0) | BIT0;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
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/* Enable SMBus MMIO. */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
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LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
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PciData8 |= BIT0;
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LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
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switch (socket_id) {
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case 0:
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/* Switch onto the First CPU Socket SMBus */
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writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x80, 0x03);
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break;
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case 1:
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/* Switch onto the Second CPU Socket SMBus */
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writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x40, 0x03);
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break;
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default:
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/* Switch off two CPU Sockets SMBus */
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writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x00, 0x03);
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break;
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}
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}
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static void restore_socket(void)
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{
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/* Switch off two CPU Sockets SMBus */
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writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x00, 0x03);
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}
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#endif
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static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, board_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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#ifdef __PRE_RAM__
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if (ConfigPtr == NULL)
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return AGESA_ERROR;
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select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId);
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Status = agesa_ReadSpd (Func, Data, ConfigPtr);
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restore_socket();
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#else
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Status = AGESA_UNSUPPORTED;
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#endif
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return Status;
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}
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