afa39105d8
This patch introduces x86_64 (64-bit) support to the payload, building upon the existing x86 (32-bit) architecture. Files necessary for 64-bit compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig option. BUG=b:242829490 TEST=Able to verify all valid combinations between coreboot and payload with this patch. Payload Entry Point Behavior with below code. +----------------+--------------------+----------------------------+ | LP_ARCH_X86_64 | Payload Entry Mode | Description | +----------------+--------------------+----------------------------+ | No | 32-bit | Direct protected mode init | +----------------+--------------------+----------------------------+ | Yes | 32-bit | Protected to long mode | +----------------+--------------------+----------------------------+ | Yes | 64-bit | Long mode initialization | +----------------+--------------------+----------------------------+ Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
150 lines
4.1 KiB
ArmAsm
150 lines
4.1 KiB
ArmAsm
/*
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*
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* Copyright 2024 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* For reference see "AMD64 Architecture Programmer's Manual Volume 2",
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* Document 24593-Rev. 3.31-July 2019 Chapter 5.3.4
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*
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* Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty
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*/
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.section .bss
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#define _PRES (1ULL << 0)
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#define _RW (1ULL << 1)
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#define _US (1ULL << 2)
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#define _A (1ULL << 5)
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#define _D (1ULL << 6)
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#define _PS (1ULL << 7)
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.section .bss.pm4le
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.global pm4le
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.align 4096
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pm4le:
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.skip 8
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.section .bss.main_page_table
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.global main_page_table
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.align 4096
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main_page_table:
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.skip 8192
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.section .bss.extra_page_table
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.global extra_page_table
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.align 4096
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extra_page_table:
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.skip 32
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/*
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* WARNING: 32-bit/64-bit Mode Compatibility for Page Table Initialization
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* This `init_page_table` function is designed to work in both 32-bit protected
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* mode AND 64-bit long mode.
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*
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* Key Considerations:
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* - Assembly Instructions: Use ONLY instructions that have the SAME binary representation
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* in both 32-bit and 64-bit modes.
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* - `.code64` Directive: We're compiling with `.code64` to ensure the assembler uses
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* the correct 64-bit version of instructions (e.g., `inc`).
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* - Register Notation:
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* - Use 64-bit register names (like `%rsi`) for register-indirect addressing to avoid
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* incorrect address size prefixes.
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* - It's safe to use `%esi` with `mov` instructions, as the high 32 bits are zeroed
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* in 64-bit mode.
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*
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* IMPORTANT:
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* Thoroughly test ANY changes to this function in BOTH 32-bit and 64-bit boot environments.
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*/
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.code64
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.section .text.init_page_table
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.globl init_page_table
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.type init_page_table, @function
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init_page_table:
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mov $0x80000001, %eax
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cpuid
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test $(1 << 26), %edx
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jnz setup_1gb
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setup_2mb:
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mov $2048, %edi
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mov $(_PRES + _RW + _US + _PS + _A + _D), %eax
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mov $0, %ecx
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mov $main_page_table, %esi
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loop_2mb:
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mov %eax, (%rsi, %rcx, 8)
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mov $0, 4(%rsi, %rcx, 8)
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add $0x200000, %eax
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inc %ecx
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cmp %edi, %ecx
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jb loop_2mb
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mov $4, %edi
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mov $main_page_table, %eax
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add $(_PRES + _RW + _US + _A), %eax
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mov $0, %ecx
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mov $extra_page_table, %esi
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fill_extra_page_table:
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mov %eax, (%rsi, %rcx, 8)
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mov $0, 4(%rsi, %rcx, 8)
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add $4096, %eax
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inc %ecx
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cmp %edi, %ecx
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jb fill_extra_page_table
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mov $extra_page_table, %eax
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jmp leave
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setup_1gb:
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mov $512, %edi
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mov $(_PRES + _RW + _US + _PS + _A + _D), %eax
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mov $0, %ebx
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mov $0, %ecx
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mov $main_page_table, %esi
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loop_1gb:
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mov %eax, (%rsi, %rcx, 8)
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mov %ebx, 4(%rsi, %rcx, 8)
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add $0x40000000, %eax
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cmp $0x40000000, %eax
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ja no_overflow_1gb
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inc %ebx
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no_overflow_1gb:
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inc %ecx
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cmp %edi, %ecx
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jb loop_1gb
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mov $main_page_table, %eax
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leave:
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or $(_PRES + _RW + _US + _A), %eax
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mov %eax, pm4le
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ret
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