91162705a6
This is an old (pre-2005) entry-level server mainboard. The code is adapted from mainboard/intel/xe7501devkit. Featured chips: - Dual socket604 - E7505 northbridge - 82801DB southbridge (with EHCI debug port) - 82870p2 PCI-X bridge - LPC47M102S-MC super-io - 512kB FWH flash (flashrom does the job well) What works: - Dual-Xeon P4/HT boot with microcode update - RAM: registered ECC DDR266 in dual-channel - PCI-X slot interrupts with ACPI and I/O apic - On-board PCI-X GbE and SCSI - ACPI power-off and wakeup with PME# Notes : - Current ACPI is more or less a mess - Interrupts do not route correctly with PIRQ - MP-table is not implemented - Issues with reboots remain (cold and warm) - Many superio devices are disabled by default - Audio codec is not investigated Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/303 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
114 lines
2.5 KiB
Plaintext
114 lines
2.5 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x04, // DSDT revision: ACPI v4.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20111103 // OEM revision
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) {
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Scope(\_SB)
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{
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Device(PCI0) {
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Name (_HID, EISAID("PNP0A03"))
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Name (_ADR, 0x00)
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Name (_PRT, Package() {
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Package() { 0x001dffff, 0, 0, 16 },
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Package() { 0x001dffff, 1, 0, 19 },
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Package() { 0x001dffff, 2, 0, 18 },
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Package() { 0x001dffff, 3, 0, 23 },
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Package() { 0x001fffff, 0, 0, 18 },
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Package() { 0x001fffff, 1, 0, 17 },
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})
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#include "acpi/e7505_sec.asl"
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OperationRegion (I750, PCI_Config, 0x00, 0x0100)
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Field (I750, ByteAcc, NoLock, Preserve)
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{
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Offset (0xC4),
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TOLM, 16, /* Top of Low Memory */
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RBAR, 16, /* REMAP_BASE */
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RLAR, 16 /* REMAP_LIMIT */
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}
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}
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#include "acpi/e7505_pri.asl"
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Device (PWBT)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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Name (_PRW, Package () { 0x08, 0x05 })
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}
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Device (SLBT)
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{
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Name (_HID, EisaId ("PNP0C0E"))
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Name (_PRW, Package () { 0x0B, 0x05 })
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}
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Device (LID0)
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{
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Name (_HID, EisaId ("PNP0C0D"))
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Name (_PRW, Package () { 0x0B, 0x05 })
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}
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}
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Scope(\_SB.PCI0)
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{
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Device(PCI1)
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{
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Name (_ADR, 0x00010000)
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Name (_PRT, Package() {
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Package() { 0x0000ffff, 0, 0, 16 },
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Package() { 0x0000ffff, 1, 0, 17 },
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})
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}
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Device(HLIB)
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{
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Name (_ADR, 0x00020000)
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Name (_PRT, Package() {
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Package() { 0x001dffff, 0, 0, 18 },
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Package() { 0x001dffff, 1, 0, 18 },
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Package() { 0x001dffff, 2, 0, 18 },
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Package() { 0x001dffff, 3, 0, 18 },
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Package() { 0x001fffff, 0, 0, 18 },
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Package() { 0x001fffff, 1, 0, 18 },
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Package() { 0x001fffff, 2, 0, 18 },
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Package() { 0x001fffff, 3, 0, 18 },
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})
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#include "acpi/p64h2.asl"
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}
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#include "acpi/i82801db.asl"
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}
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#include "acpi/power.asl"
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}
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