91b027a351
This patch adds support for logging wake source information in gsmi callbacks. With this change, all the elog logging infrastructure can be used for S0ix as well as S3 on cannonlake. BUG=b:124131938 BRANCH=none TEST=Verified that the wake events are logged during the S0ix resume: 6 | 2019-03-04 17:03:13 | S0ix Enter 7 | 2019-03-04 17:03:17 | S0ix Exit 8 | 2019-03-04 17:03:17 | Wake Source | RTC Alarm | 0 9 | 2019-03-04 17:03:55 | S0ix Enter 10 | 2019-03-04 17:03:56 | S0ix Exit 11 | 2019-03-04 17:03:56 | Wake Source | GPE # | 21 12 | 2019-03-04 17:04:36 | S0ix Enter 13 | 2019-03-04 17:04:45 | S0ix Exit 14 | 2019-03-04 17:04:45 | Wake Source | GPE # | 112 15 | 2019-03-04 17:05:01 | S0ix Enter 16 | 2019-03-04 17:05:09 | S0ix Exit 17 | 2019-03-04 17:05:09 | Wake Source | Power Button | 0 Change-Id: Id627843e22c2524dfa94395b780cf2134f386137 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
133 lines
3.6 KiB
C
133 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Intel Corporation.
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootstate.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <stdint.h>
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#include <elog.h>
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#include <intelblocks/pmclib.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
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{
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int i;
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gpe0_sts &= gpe0_en;
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for (i = 0; i <= 31; i++) {
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
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}
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}
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static void pch_log_wake_source(struct chipset_power_state *ps)
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{
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/* Power Button */
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if (ps->pm1_sts & PWRBTN_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
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/* RTC */
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if (ps->pm1_sts & RTC_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
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/* PCI Express (TODO: determine wake device) */
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if (ps->pm1_sts & PCIEXPWAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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/* PME (TODO: determine wake device) */
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if (ps->gpe0_sts[GPE_STD] & PME_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
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/* Internal PME (TODO: determine wake device) */
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if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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/* SMBUS Wake */
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if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
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/* Log GPIO events in set 1-3 */
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
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/* Treat the STD as an extension of GPIO to obtain visibility. */
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
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}
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static void pch_log_power_and_resets(struct chipset_power_state *ps)
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{
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/* Thermal Trip */
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if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
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elog_add_event(ELOG_TYPE_THERM_TRIP);
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/* PWR_FLR Power Failure */
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if (ps->gen_pmcon_b & PWR_FLR)
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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/* SUS Well Power Failure */
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if (ps->gen_pmcon_b & SUS_PWR_FLR)
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elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
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/* TCO Timeout */
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if (ps->prev_sleep_state != ACPI_S3 &&
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ps->tco2_sts & TCO_STS_SECOND_TO)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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if (ps->pm1_sts & PRBTNOR_STS)
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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/* RTC reset */
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if (ps->gen_pmcon_b & RTC_BATTERY_DEAD)
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elog_add_event(ELOG_TYPE_RTC_RESET);
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/* Host Reset Status */
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if (ps->gen_pmcon_b & HOST_RST_STS)
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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/* ACPI Wake Event */
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if (ps->prev_sleep_state != ACPI_S0)
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
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}
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static void pch_log_state(void *unused)
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{
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struct chipset_power_state *ps = pmc_get_power_state();
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if (!ps) {
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printk(BIOS_ERR, "chipset_power_state not found!\n");
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return;
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}
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/* Power and Reset */
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pch_log_power_and_resets(ps);
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/* Wake Sources */
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if (ps->prev_sleep_state > ACPI_S0)
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pch_log_wake_source(ps);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL);
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void elog_gsmi_cb_platform_log_wake_source(void)
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{
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struct chipset_power_state ps;
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pmc_fill_pm_reg_info(&ps);
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pch_log_wake_source(&ps);
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}
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