925ad2efad
Like on kirby, this header had a single constant in it that was actually used. This change moves that constant inline and gets rid of the header file. Change-Id: Ibe380396f72fddb121fb6ceb3cee24f1b9a85738 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64163 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4420 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
397 lines
10 KiB
C
397 lines
10 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <cbmem.h>
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#include <delay.h>
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#include <edid.h>
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#include <vbe.h>
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#include <boot/coreboot_tables.h>
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <cpu/samsung/exynos5420/tmu.h>
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#include <cpu/samsung/exynos5420/clk.h>
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#include <cpu/samsung/exynos5420/cpu.h>
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#include <cpu/samsung/exynos5420/gpio.h>
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#include <cpu/samsung/exynos5420/power.h>
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#include <cpu/samsung/exynos5420/i2c.h>
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#include <cpu/samsung/exynos5420/dp-core.h>
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#include <drivers/parade/ps8625/ps8625.h>
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#include <ec/google/chromeec/ec.h>
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#include <stdlib.h>
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/* convenient shorthand (in MB) */
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#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
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#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
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#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
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static struct edid edid = {
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.ha = 1366,
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.va = 768,
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.bpp = 16,
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.x_resolution = 1366,
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.y_resolution = 768,
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.bytes_per_line = 2 * 1366
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};
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static const struct parade_write parade_writes[] = {
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{ 0x02, 0xa1, 0x01 }, /* HPD low */
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/*
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* SW setting
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* [1:0] SW output 1.2V voltage is lower to 96%
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*/
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{ 0x04, 0x14, 0x01 },
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/*
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* RCO SS setting
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* [5:4] = b01 0.5%, b10 1%, b11 1.5%
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*/
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{ 0x04, 0xe3, 0x20 },
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{ 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */
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/*
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* RPHY Setting
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* [3:2] CDR tune wait cycle before
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* measure for fine tune b00: 1us,
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* 01: 0.5us, 10:2us, 11:4us.
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*/
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{ 0x04, 0x8a, 0x0c },
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{ 0x04, 0x89, 0x08 }, /* [3] RFD always on */
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/*
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* CTN lock in/out:
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* 20000ppm/80000ppm. Lock out 2
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* times.
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*/
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{ 0x04, 0x71, 0x2d },
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/*
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* 2.7G CDR settings
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* NOF=40LSB for HBR CDR setting
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*/
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{ 0x04, 0x7d, 0x07 },
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{ 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */
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{ 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */
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/*
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* 1.62G CDR settings
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* [5:2]NOF=64LSB [1:0]DCO scale is 2/5
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*/
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{ 0x04, 0xc0, 0x12 },
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{ 0x04, 0xc1, 0x92 }, /* Gitune=-37% */
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{ 0x04, 0xc2, 0x1c }, /* Fbstep=100% */
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{ 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */
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/*
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* RPIO Setting
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* [7:4] LVDS driver bias current :
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* 75% (250mV swing)
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*/
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{ 0x04, 0x00, 0xb0 },
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/*
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* [7:6] Right-bar GPIO output strength is 8mA
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*/
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{ 0x04, 0x15, 0x40 },
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/* EQ Training State Machine Setting */
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{ 0x04, 0x54, 0x10 }, /* RCO calibration start */
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/* [4:0] MAX_LANE_COUNT set to one lane */
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{ 0x01, 0x02, 0x81 },
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/* [4:0] LANE_COUNT_SET set to one lane */
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{ 0x01, 0x21, 0x81 },
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{ 0x00, 0x52, 0x20 },
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{ 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */
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{ 0x00, 0x62, 0x41 },
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/* Counter number, add 1ms counter delay */
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{ 0x00, 0xf6, 0x01 },
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/*
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* [6]PWM function control by
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* DPCD0040f[7], default is PWM
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* block always works.
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*/
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{ 0x00, 0x77, 0x06 },
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/*
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* 04h Adjust VTotal tolerance to
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* fix the 30Hz no display issue
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*/
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{ 0x00, 0x4c, 0x04 },
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/* DPCD00400='h00, Parade OUI = 'h001cf8 */
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{ 0x01, 0xc0, 0x00 },
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{ 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */
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{ 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */
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/*
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* DPCD403~408 = ASCII code
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* D2SLV5='h4432534c5635
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*/
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{ 0x01, 0xc3, 0x44 },
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{ 0x01, 0xc4, 0x32 }, /* DPCD404 */
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{ 0x01, 0xc5, 0x53 }, /* DPCD405 */
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{ 0x01, 0xc6, 0x4c }, /* DPCD406 */
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{ 0x01, 0xc7, 0x56 }, /* DPCD407 */
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{ 0x01, 0xc8, 0x35 }, /* DPCD408 */
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/*
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* DPCD40A, Initial Code major revision
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* '01'
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*/
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{ 0x01, 0xca, 0x01 },
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/* DPCD40B, Initial Code minor revision '05' */
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{ 0x01, 0xcb, 0x05 },
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/* DPCD720, Select external PWM */
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{ 0x01, 0xa5, 0x80 },
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/*
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* Set LVDS output as 6bit-VESA mapping,
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* single LVDS channel
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*/
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{ 0x01, 0xcc, 0x13 },
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/* Enable SSC set by register */
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{ 0x02, 0xb1, 0x20 },
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/*
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* Set SSC enabled and +/-1% central
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* spreading
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*/
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{ 0x04, 0x10, 0x16 },
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/* MPU Clock source: LC => RCO */
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{ 0x04, 0x59, 0x60 },
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{ 0x04, 0x54, 0x14 }, /* LC -> RCO */
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{ 0x02, 0xa1, 0x91 } /* HPD high */
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};
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/* TODO: transplanted DP stuff, clean up once we have something that works */
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static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */
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static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */
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static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */
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static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */
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static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */
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static void parade_dp_bridge_setup(void)
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{
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gpio_set_value(dp_pd_l, 1);
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gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT);
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gpio_set_pull(dp_pd_l, GPIO_PULL_NONE);
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gpio_set_value(dp_rst_l, 0);
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gpio_cfg_pin(dp_rst_l, GPIO_OUTPUT);
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gpio_set_pull(dp_rst_l, GPIO_PULL_NONE);
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udelay(10);
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gpio_set_value(dp_rst_l, 1);
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gpio_cfg_pin(dp_hpd, GPIO_INPUT);
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/* De-assert PD (and possibly RST) to power up the bridge. */
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gpio_set_value(dp_pd_l, 1);
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gpio_set_value(dp_rst_l, 1);
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/* Hang around for the bridge to come up. */
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mdelay(40);
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/* Configure the bridge chip. */
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exynos_pinmux_i2c7();
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i2c_init(7, 100000, 0x00);
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parade_ps8625_bridge_setup(7, 0x48,
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parade_writes,
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ARRAY_SIZE(parade_writes));
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}
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/*
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* This delay is T3 in the LCD timing spec (defined as >200ms). We set
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* this down to 60ms since that's the approximate maximum amount of time
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* it'll take a bridge to start outputting LVDS data. The delay of
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* >200ms is just a conservative value to avoid turning on the backlight
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* when there's random LCD data on the screen. Shaving 140ms off the
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* boot is an acceptable trade-off.
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*/
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#define LCD_T3_DELAY_MS 60
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#define LCD_T5_DELAY_MS 10
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#define LCD_T6_DELAY_MS 10
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static void backlight_pwm(void)
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{
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/*Configure backlight PWM as a simple output high (100% brightness) */
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gpio_direction_output(bl_pwm, 1);
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udelay(LCD_T6_DELAY_MS * 1000);
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}
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static void backlight_en(void)
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{
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/* Configure GPIO for LCD_BL_EN */
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gpio_direction_output(bl_en, 1);
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}
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//static struct video_info smdk5420_dp_config = {
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static struct video_info dp_video_info = {
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/* FIXME: fix video_info struct to use const for name */
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.name = (char *)"eDP-LVDS NXP PTN3460",
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.h_sync_polarity = 0,
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.v_sync_polarity = 0,
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.interlaced = 0,
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.color_space = COLOR_RGB,
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.dynamic_range = VESA,
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.ycbcr_coeff = COLOR_YCBCR601,
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.color_depth = COLOR_8,
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.link_rate = LINK_RATE_2_70GBPS,
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.lane_count = LANE_COUNT2,
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};
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/* FIXME: move some place more appropriate */
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#define EXYNOS5420_DP1_BASE 0x145b0000
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#define MAX_DP_TRIES 5
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/*
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* This function disables the USB3.0 PLL to save power
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*/
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static void disable_usb30_pll(void)
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{
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enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11;
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gpio_direction_output(usb3_pll_l, 0);
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}
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static void gpio_init(void)
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{
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/* Set up the I2C busses. */
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exynos_pinmux_i2c2();
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exynos_pinmux_i2c4();
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exynos_pinmux_i2c7();
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exynos_pinmux_i2c8();
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exynos_pinmux_i2c9();
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exynos_pinmux_i2c10();
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}
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enum {
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FET_CTRL_WAIT = 3 << 2,
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FET_CTRL_ADENFET = 1 << 1,
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FET_CTRL_ENFET = 1 << 0
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};
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static void tps65090_thru_ec_fet_set(int index)
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{
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uint8_t value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET;
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if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) {
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printk(BIOS_ERR,
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"Error sending i2c pass through command to EC.\n");
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return;
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}
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}
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static void lcd_vdd(void)
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{
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/* Enable FET6, lcd panel */
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tps65090_thru_ec_fet_set(6);
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}
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static void backlight_vdd(void)
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{
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/* Enable FET1, backlight */
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tps65090_thru_ec_fet_set(1);
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}
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/* this happens after cpu_init where exynos resources are set */
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static void mainboard_init(device_t dev)
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{
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struct s5p_dp_device dp_device = {
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.base = (struct exynos5_dp *)EXYNOS5420_DP1_BASE,
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.video_info = &dp_video_info,
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};
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void *fb_addr = (void *)(get_fb_base_kb() * KiB);
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gpio_init();
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tmu_init(&exynos5420_tmu_info);
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/* Clock Gating all the unused IP's to save power */
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clock_gate();
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/* Disable USB3.0 PLL to save 250mW of power */
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disable_usb30_pll();
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set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
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/*
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* The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000
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* should be 0 according to the datasheet, but has experimentally
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* been found to come up as 3. This means FIMD SYSMMU is on by
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* default on Exynos5420. For now we are disabling FIMD SYSMMU.
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*/
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writel(0x0, (void *)0x14640000);
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writel(0x0, (void *)0x14680000);
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lcd_vdd();
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parade_dp_bridge_setup();
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dp_controller_init(&dp_device);
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udelay(LCD_T3_DELAY_MS * 1000);
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backlight_vdd();
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backlight_pwm();
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backlight_en();
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// Uncomment to get excessive GPIO output:
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// gpio_info();
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}
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#if !CONFIG_DYNAMIC_CBMEM
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void get_cbmem_table(uint64_t *base, uint64_t *size)
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{
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*size = CONFIG_COREBOOT_TABLES_SIZE;
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*base = CONFIG_SYS_SDRAM_BASE +
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((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
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CONFIG_COREBOOT_TABLES_SIZE;
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}
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#endif
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = &mainboard_init;
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#if !CONFIG_DYNAMIC_CBMEM
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/* set up coreboot tables */
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cbmem_initialize();
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#endif
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/* set up dcache and MMU */
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/* FIXME: this should happen via resource allocator */
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exynos5420_config_l2_cache();
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mmu_init();
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mmu_config_range(0, DRAM_START, DCACHE_OFF);
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mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
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mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
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dcache_invalidate_all();
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dcache_mmu_enable();
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/* this is going to move, but we must have it now and we're
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* not sure where */
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exception_init();
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const unsigned epll_hz = 192000000;
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const unsigned sample_rate = 48000;
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const unsigned lr_frame_size = 256;
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clock_epll_set_rate(epll_hz);
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clock_select_i2s_clk_source();
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clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);
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power_enable_xclkout();
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}
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struct chip_operations mainboard_ops = {
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.name = "Samsung/Google ARM Chromebook",
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.enable_dev = mainboard_enable,
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};
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