925e3896d0
AMD GPIO driver will not load if IRQ is not set. As a consequence, it does not clear the interrupt when waking from S0i3. BUG=178728116 TEST=Perform 2 S0i3 cycles, confirming second cycle does not return instantly due to first interrupt not being cleared. Change-Id: I3072263e8e68f939a47ed4125444c60133087824 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/amd_pci_util.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <soc/acpi.h>
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#include <string.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/*
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*/
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static uint8_t fch_pic_routing[0x80];
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static uint8_t fch_apic_routing[0x80];
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_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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"PIC and APIC FCH interrupt tables must be the same size");
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/*
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* This controls the device -> IRQ routing.
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*
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* Hardcoded IRQs:
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* 0: timer < soc/amd/common/acpi/lpc.asl
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* 1: i8042 - Keyboard
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* 2: cascade
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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*/
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static const struct fch_irq_routing {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} majolica_fch[] = {
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{ PIRQ_A, PIRQ_NC, PIRQ_NC },
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{ PIRQ_B, PIRQ_NC, PIRQ_NC },
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{ PIRQ_C, PIRQ_NC, PIRQ_NC },
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{ PIRQ_D, PIRQ_NC, PIRQ_NC },
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{ PIRQ_E, PIRQ_NC, PIRQ_NC },
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{ PIRQ_F, PIRQ_NC, PIRQ_NC },
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{ PIRQ_G, PIRQ_NC, PIRQ_NC },
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{ PIRQ_H, PIRQ_NC, PIRQ_NC },
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{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
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{ PIRQ_SD, PIRQ_NC, PIRQ_NC },
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{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
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{ PIRQ_SATA, PIRQ_NC, PIRQ_NC },
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{ PIRQ_EMMC, PIRQ_NC, PIRQ_NC },
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{ PIRQ_GPIO, 7, 7 },
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{ PIRQ_I2C2, PIRQ_NC, PIRQ_NC },
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{ PIRQ_I2C3, PIRQ_NC, PIRQ_NC },
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{ PIRQ_UART0, 4, 4 },
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{ PIRQ_UART1, 3, 3 },
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/* The MISC registers are not interrupt numbers */
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{ PIRQ_MISC, 0xfa, 0x00 },
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{ PIRQ_MISC0, 0x91, 0x00 },
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{ PIRQ_HPET_L, 0x00, 0x00 },
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{ PIRQ_HPET_H, 0x00, 0x00 },
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};
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static void init_tables(void)
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{
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const struct fch_irq_routing *entry;
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int i;
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memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
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memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
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for (i = 0; i < ARRAY_SIZE(majolica_fch); i++) {
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entry = majolica_fch + i;
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fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
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fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
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}
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}
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static void pirq_setup(void)
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{
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intr_data_ptr = fch_apic_routing;
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picr_data_ptr = fch_pic_routing;
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}
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static void mainboard_init(void *chip_info)
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{
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}
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static void mainboard_enable(struct device *dev)
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{
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init_tables();
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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