9265f89f4e
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
47 lines
1.3 KiB
Makefile
47 lines
1.3 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 secunet Security Networks AG
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y)
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romstage-y += early_init.c
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romstage-y += early_reset.c
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romstage-y += raminit.c
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romstage-y += raminit_rcomp_calibration.c
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romstage-y += raminit_receive_enable_calibration.c
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romstage-y += raminit_read_write_training.c
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romstage-y += pcie.c
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romstage-y += thermal.c
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romstage-y += igd.c
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romstage-y += pm.c
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romstage-y += ram_calc.c
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romstage-y += iommu.c
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romstage-y += romstage.c
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ramstage-y += acpi.c
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ramstage-y += ram_calc.c
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ramstage-y += northbridge.c
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ramstage-y += gma.c
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smm-y += ../../../cpu/x86/lapic/apic_timer.c
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postcar-y += ram_calc.c
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romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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endif
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