Files
system76-coreboot/src/superio/ite/it8728f/chip.h
Edward O'Callaghan 946bee1c34 superio/ite/it8728f: RAMstage PNP configuration component
Provide devicetree.cb RAMstage configuration of this superio component.

Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5668
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-11 17:20:31 +02:00

35 lines
1.2 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_ITE_IT8728F_CHIP_H
#define SUPERIO_ITE_IT8728F_CHIP_H
struct superio_ite_it8728f_config {
/* HWM configuration registers */
uint8_t hwm_ctl_register;
uint8_t hwm_main_ctl_register;
uint8_t hwm_adc_temp_chan_en_reg;
uint8_t hwm_fan1_ctl_pwm;
uint8_t hwm_fan2_ctl_pwm;
uint8_t hwm_fan3_ctl_pwm;
};
#endif /* SUPERIO_ITE_IT8728F_CHIP_H */