949d666b5c
This commit adds device name to ACPI name bindings for various entries in the devicetree. BUG=b:72121803 Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/cpu.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = stoney_init_cpus,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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};
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static const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case EHCI1_DEVFN:
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return "EHC0";
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case LPC_DEVFN:
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return "LPCB";
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case SATA_DEVFN:
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return "STCR";
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case SD_DEVFN:
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return "SDCN";
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case SMBUS_DEVFN:
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return "SBUS";
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case XHCI_DEVFN:
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return "XHC0";
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default:
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return NULL;
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}
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};
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struct device_operations pci_domain_ops = {
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.read_resources = domain_read_resources,
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.set_resources = domain_set_resources,
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.enable_resources = domain_enable_resources,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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.acpi_name = soc_acpi_name,
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};
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static void enable_dev(device_t dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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dev->ops = &pci_domain_ops;
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &cpu_bus_ops;
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else if (dev->path.type == DEVICE_PATH_PCI)
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sb_enable(dev);
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}
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static void soc_init(void *chip_info)
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{
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southbridge_init(chip_info);
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setup_bsp_ramtop();
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}
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static void soc_final(void *chip_info)
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{
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southbridge_final(chip_info);
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fam15_finalize(chip_info);
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}
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struct chip_operations soc_amd_stoneyridge_ops = {
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CHIP_NAME("AMD StoneyRidge SOC")
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.enable_dev = &enable_dev,
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.init = &soc_init,
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.final = &soc_final
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};
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static void earliest_ramstage(void *unused)
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{
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post_code(0x46);
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if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
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psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
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post_code(0x47);
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do_agesawrapper(agesawrapper_amdinitenv, "amdinitenv");
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}
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BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL);
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