9550e97304
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
84 lines
2.4 KiB
Plaintext
84 lines
2.4 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* DefinitionBlock Statement */
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#include <arch/acpi.h>
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DefinitionBlock (
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"DSDT.AML", /* Output filename */
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"DSDT", /* Signature */
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0x02, /* DSDT Revision, needs to be 2 for 64bit */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
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/* Globals for the platform */
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#include "acpi/mainboard.asl"
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/* Describe the USB Overcurrent pins */
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#include "acpi/usb_oc.asl"
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/* PCI IRQ mapping for the Southbridge */
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#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
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/* Describe the processor tree (\_SB) */
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#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
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/* Contains the supported sleep states for this chipset */
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#include <southbridge/amd/common/acpi/sleepstates.asl>
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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#include "acpi/sleep.asl"
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/* System Bus */
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Scope(\_SB) { /* Start \_SB scope */
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
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#include "acpi/routing.asl"
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Device(PWRB) {
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Name(_HID, EISAID("PNP0C0C"))
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Name(_UID, 0xAA)
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Name(_PRW, Package () {3, 0x04})
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Name(_STA, 0x0B)
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}
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Device(PCI0) {
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/* Describe the AMD Northbridge */
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#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
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/* Describe the AMD Fusion Controller Hub Southbridge */
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#include <southbridge/amd/pi/hudson/acpi/fch.asl>
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}
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/* Describe PCI INT[A-H] for the Southbridge */
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#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
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} /* End \_SB scope */
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/* Describe SMBUS for the Southbridge */
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#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
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/* Define the General Purpose Events for the platform */
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#include "acpi/gpe.asl"
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/* Define the System Indicators for the platform */
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#include "acpi/si.asl"
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}
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/* End of ASL file */
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