95b6611c18
This set adds support for the SuperMicro H8QGI mainboard. It is a publicly available 4 socket board using AMD Family 10 cpus and AMD SR5650 and SB700 bridges. Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/108 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
230 lines
6.4 KiB
C
Executable File
230 lines
6.4 KiB
C
Executable File
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "Porting.h"
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#include "AGESA.h"
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#include "amdlib.h"
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <device/pci_ids.h>
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AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
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#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
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/* SP5100 GPIO 53-56 contoled by SMBUS PCI_Reg 0x52 */
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#define SP5100_GPIO53_56 0x52
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/**
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* TODO not support all GPIO yet
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* @param reg -GPIO Cntrl Register
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* @param out -GPIO bitmap
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* @param out -GPIO enable bitmap
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*/
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static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
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{
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u8 value;
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device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
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value = pci_read_config8(sm_dev, reg);
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value &= ~(enable);
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value |= out;
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value &= ~(enable << 4);
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pci_write_config8(sm_dev, reg, value);
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}
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/*-----------------------------------------------------------------------------
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*
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* SPD address table - porting required
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*/
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static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm
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/* socket 0 */
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{
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{0xAE, 0xAC},
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{0xAA, 0xA8},
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{0xA6, 0xA4},
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{0xA2, 0xA0},
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},
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/* socket 1 */
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{
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{0xAE, 0xAC},
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{0xAA, 0xA8},
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{0xA6, 0xA4},
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{0xA2, 0xA0},
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},
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/* socket 2 */
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{
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{0xAE, 0xAC},
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{0xAA, 0xA8},
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{0xA6, 0xA4},
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{0xA2, 0xA0},
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},
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/* socket 3 */
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{
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{0xAE, 0xAC},
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{0xAA, 0xA8},
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{0xA6, 0xA4},
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{0xA2, 0xA0},
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},
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};
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/*-----------------------------------------------------------------------------
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*
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* readSmbusByteData - read a single SPD byte from any offset
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*/
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static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
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{
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unsigned int status;
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UINT64 limit;
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address |= 1; // set read bit
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outb(0xFF, iobase + 0); // clear error status
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outb(0x1F, iobase + 1); // clear error status
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outb(offset, iobase + 3); // offset in eeprom
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outb(address, iobase + 4); // slave address and read bit
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outb(0x48, iobase + 2); // read byte command
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// time limit to avoid hanging for unexpected error status (should never happen)
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limit = __rdtsc () + 2000000000 / 10;
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for (;;)
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{
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status = inb(iobase);
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if (__rdtsc () > limit) break;
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if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
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if ((status & 1) == 1) continue; // HostBusy set, keep waiting
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break;
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}
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buffer [0] = inb(iobase + 5);
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if (status == 2) status = 0; // check for done with no errors
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return status;
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}
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/*-----------------------------------------------------------------------------
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*
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* readSmbusByte - read a single SPD byte from the default offset
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* this function is faster function readSmbusByteData
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*/
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static int readSmbusByte (int iobase, int address, char *buffer)
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{
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unsigned int status;
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UINT64 limit;
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outb(0xFF, iobase + 0); // clear error status
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outb(0x44, iobase + 2); // read command
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// time limit to avoid hanging for unexpected error status
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limit = __rdtsc () + 2000000000 / 10;
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for (;;)
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{
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status = inb(iobase);
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if (__rdtsc () > limit) break;
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if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
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if ((status & 1) == 1) continue; // HostBusy set, keep waiting
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break;
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}
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buffer [0] = inb(iobase + 5);
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if (status == 2) status = 0; // check for done with no errors
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return status;
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}
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/*---------------------------------------------------------------------------
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*
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* readspd - Read one or more SPD bytes from a DIMM.
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* Start with offset zero and read sequentially.
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* Optimization relies on autoincrement to avoid
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* sending offset for every byte.
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* Reads 128 bytes in 7-8 ms at 400 KHz.
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*/
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static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
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{
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int index, error;
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/* read the first byte using offset zero */
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error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
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if (error) {
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return error;
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}
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/* read the remaining bytes using auto-increment for speed */
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for (index = 1; index < count; index++)
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{
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error = readSmbusByte (iobase, SmbusSlaveAddress, buffer + index);
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if (error)
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return error;
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}
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return 0;
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}
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static void writePmReg (int reg, int data)
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{
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outb(reg, 0xCD6);
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outb(data, 0xCD7);
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}
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static void setupFch (int ioBase)
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{
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writePmReg (0x2D, ioBase >> 8);
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writePmReg (0x2C, ioBase | 1);
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writePmReg (0x29, 0x80);
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writePmReg (0x28, 0x61);
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outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz
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}
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AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
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{
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int spdAddress, ioBase;
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u8 i2c_channel;
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device_t sm_dev;
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if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
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if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
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if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
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i2c_channel = (UINT8) info->SocketId;
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/* set ght i2c channel
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* GPIO54,53 control the HC4052 S1,S0
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* S1 S0 true table
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* 0 0 channel 1 (Socket1)
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* 0 1 channel 2 (Socket2)
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* 1 0 channel 3 (Socket3)
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* 1 1 channel 4 (Socket4)
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*/
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sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03);
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spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
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if (spdAddress == 0)
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return AGESA_ERROR;
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/*
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* SMBus Base Address was set during southbridge early setup.
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* e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000
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*/
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sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0);
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ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0);
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setupFch(ioBase);
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return readspd(ioBase, spdAddress, (void *)info->Buffer, 256);
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}
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