97c7c6bbb6
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
32 lines
796 B
Makefile
32 lines
796 B
Makefile
ramstage-y += model_2065x_init.c
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subdirs-y += ../../x86/name
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../intel/turbo
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subdirs-y += ../../intel/microcode
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm/gen1
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subdirs-y += ../common
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ramstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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postcar-y += tsc_freq.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
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ramstage-y += acpi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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romstage-y += stage_cache.c
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ramstage-y += stage_cache.c
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postcar-y += stage_cache.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
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cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
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postcar-y += ../car/non-evict/exit_car.S
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romstage-y += ../car/romstage.c
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