97ea346fdf
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I77275adb7c15b242e319805b8a60b7755fa25db5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
180 lines
6.3 KiB
C
180 lines
6.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <AGESA.h>
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#include <amdlib.h>
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/* Define AMD Ontario APPU SSID/SVID */
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#define AMD_APU_SVID 0x1022
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#define AMD_APU_SSID 0x1234
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
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PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
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PciData |= 1 << 7; // set NP (non-posted) bit
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
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PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; // last address before non-posted range
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32) MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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void amd_initmmio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/*
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Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
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Address MSR register.
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*/
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
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/* Set Ontario Link Data */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
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PciData = 0x01308002;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4);
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PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;
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LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
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MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
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LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
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/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
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MsrReg = 0;
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LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader);
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}
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void amd_initenv(void)
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{
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AMD_INTERFACE_PARAMS AmdParamStruct;
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PCI_ADDR PciAddress;
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UINT32 PciValue;
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/* Initialize Subordinate Bus Number and Secondary Bus Number
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* In platform BIOS this address is allocated by PCI enumeration code
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Modify D1F0x18
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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/* Write to D1F0x18 */
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x00010100;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize GMM Base Address for Legacy Bridge Mode
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* Modify B1D5F0x18
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*/
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PciAddress.Address.Bus = 1;
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PciAddress.Address.Device = 5;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize FB Base Address for Legacy Bridge Mode
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* Modify B1D5F0x10
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*/
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PciAddress.Address.Register = 0x10;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x80000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize GMM Base Address for Pcie Mode
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* Modify B0D1F0x18
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize FB Base Address for Pcie Mode
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* Modify B0D1F0x10
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*/
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PciAddress.Address.Register = 0x10;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x80000000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize MMIO Base and Limit Address
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* Modify B0D1F0x20
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x20;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x96009600;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize MMIO Prefetchable Memory Limit and Base
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* Modify B0D1F0x24
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*/
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PciAddress.Address.Register = 0x24;
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LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x8FF18001;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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}
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