9c29cfae8c
The ARM CPUs we know of don't have CPU microcode updates, so don't show the selection in Kconfig. Also simplify (and fix) the microcode selection in the Makefile that would try to include microcode even though none is available. Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2540 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
159 lines
4.7 KiB
Plaintext
159 lines
4.7 KiB
Plaintext
# Warning: This file is included whether or not the if is here.
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# The if controls how the evaluation occurs.
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# (See also src/Kconfig)
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if ARCH_ARMV7
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source src/cpu/armltd/Kconfig
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source src/cpu/samsung/Kconfig
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endif # ARCH_ARM
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if ARCH_X86
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source src/cpu/amd/Kconfig
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source src/cpu/intel/Kconfig
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source src/cpu/via/Kconfig
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source src/cpu/x86/Kconfig
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config CACHE_AS_RAM
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bool
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select DEFAULT_EARLY_CONSOLE
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default !ROMCC
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config DCACHE_RAM_BASE
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hex
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config DCACHE_RAM_SIZE
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hex
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# FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better
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# yet be dropped completely.
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config MAX_PHYSICAL_CPUS
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int
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depends on CPU_AMD_MODEL_10XXX || CPU_AMD_MODEL_FXX || CPU_AMD_AGESA
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default 1
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config SMP
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bool
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default y if MAX_CPUS != 1
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default n
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help
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This option is used to enable certain functions to make coreboot
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work correctly on symmetric multi processor (SMP) systems.
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config AP_SIPI_VECTOR
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hex
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default 0xfffff000
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help
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This must equal address of ap_sipi_vector from bootblock build.
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config MMX
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bool
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help
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Select MMX in your socket or model Kconfig if your CPU has MMX
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streaming SIMD instructions. ROMCC can build more efficient
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code if it can spill to MMX registers.
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config SSE
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bool
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help
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Select SSE in your socket or model Kconfig if your CPU has SSE
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streaming SIMD instructions. ROMCC can build more efficient
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code if it can spill to SSE (aka XMM) registers.
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config SSE2
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bool
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default n
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help
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Select SSE2 in your socket or model Kconfig if your CPU has SSE2
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streaming SIMD instructions. Some parts of coreboot can be built
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with more efficient code if SSE2 instructions are available.
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endif # ARCH_X86
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config CPU_MICROCODE_IN_CBFS
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bool
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default n
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choice
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prompt "Include CPU microcode in CBFS" if ARCH_X86
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default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS
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default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS
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config CPU_MICROCODE_CBFS_GENERATE
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bool "Generate from tree"
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help
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Select this option if you want microcode updates to be assembled when
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building coreboot and included in the final image as a separate CBFS
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file. Microcode will not be hard-coded into ramstage.
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The microcode file and may be removed from the ROM image at a later
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time with cbfstool, if desired.
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If unsure, select this option.
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config CPU_MICROCODE_CBFS_EXTERNAL
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bool "Include external microcode file"
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help
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Select this option if you want to include an external file containing
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the CPU microcode. This will be included as a separate file in CBFS.
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A word of caution: only select this option if you are sure the
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microcode that you have is newer than the microcode shipping with
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coreboot.
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The microcode file and may be removed from the ROM image at a later
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time with cbfstool, if desired.
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If unsure, select "Generate from tree"
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config CPU_MICROCODE_CBFS_NONE
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bool "Do not include microcode updates"
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help
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Select this option if you do not want CPU microcode included in CBFS.
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Note that for some CPUs, the microcode is hard-coded into the source
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tree and is not loaded from CBFS. In this case, microcode will still
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be updated. There is a push to move all microcode to CBFS, but this
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change is not implemented for all CPUs.
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This option currently applies to:
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- Intel SandyBridge/IvyBridge
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- VIA Nano
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Microcode may be added to the ROM image at a later time with cbfstool,
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if desired.
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If unsure, select "Generate from tree"
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The GOOD:
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Microcode updates intend to solve issues that have been discovered
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after CPU production. The expected effect is that systems work as
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intended with the updated microcode, but we have also seen cases where
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issues were solved by not applying microcode updates.
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The BAD:
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Note that some operating system include these same microcode patches,
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so you may need to also disable microcode updates in your operating
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system for this option to have an effect.
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The UGLY:
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A word of CAUTION: some CPUs depend on microcode updates to function
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correctly. Not updating the microcode may leave the CPU operating at
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less than optimal performance, or may cause outright hangups.
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There are CPUs where coreboot cannot properly initialize the CPU
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without microcode updates
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For example, if running with the factory microcode, some Intel
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SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
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will hang when changing the frequency.
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Make sure you have a way of flashing the ROM externally before
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selecting this option.
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endchoice
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config CPU_MICROCODE_FILE
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string "Path and filename of CPU microcode"
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depends on CPU_MICROCODE_CBFS_EXTERNAL
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default "cpu_microcode.bin"
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help
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The path and filename of the file containing the CPU microcode.
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