9aa7a25c2d
Enable SPI dTPM using eSPI bus. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I18ca41c143ade024ee2840b619ba777b22a2a86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
116 lines
3.3 KiB
Plaintext
116 lines
3.3 KiB
Plaintext
chip soc/intel/alderlake
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# USB configuration
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC3)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
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register "sata_salp_support" = "1"
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register "sata_ports_enable" = "{
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[0] = 1,
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[1] = 1,
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}"
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register "sata_ports_dev_slp" = "{
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[0] = 1,
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[1] = 1,
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}"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoPci,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80)
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# Clock source is shared hence marked as free running.
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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register "pch_pcie_rp[PCH_RP(10)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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.pcie_rp_aspm = ASPM_DISABLE,
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}"
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register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
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register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
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# Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80)
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# Clock source is shared hence marked as free running.
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
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}"
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register "cpu_pcie_rp[CPU_RP(2)]" = "{
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
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}"
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register "cpu_pcie_rp[CPU_RP(3)]" = "{
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
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}"
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device domain 0 on
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device ref pcie5 on end
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device ref igpu on end
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device ref dtt on end
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device ref pcie4_0 on end
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device ref pcie4_1 on end
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device ref crashlog off end
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device ref ish on end
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device ref ufs on end
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device ref xhci on end
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device ref heci1 on end
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device ref sata on end
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device ref pcie_rp5 on end
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device ref pcie_rp6 on end
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device ref pcie_rp7 on end
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device ref pcie_rp8 on end
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device ref pcie_rp9 on end
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device ref pcie_rp10 on end
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device ref uart0 on end
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device ref uart1 on end
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device ref pch_espi on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device ref p2sb on end
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device ref hda on end
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device ref smbus on end
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end
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end
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