9adc33d0d0
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
25 lines
612 B
Plaintext
25 lines
612 B
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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Device(PCI0) {
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Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
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Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
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/* Operating System Capabilities Method */
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Method(_OSC, 4) {
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CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */
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/* Check for proper PCI/PCIe UUID */
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If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
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/* Let OS control everything */
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Return (Arg3)
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} Else {
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CDW1 |= 4 /* Unrecognized UUID */
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Return (Arg3)
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}
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}
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/* 0:14.3 - LPC */
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#include <soc/amd/common/acpi/lpc.asl>
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} /* End PCI0 scope */
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