9aebc19182
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
28 lines
708 B
C
28 lines
708 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <gpio.h>
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#include "gpio.h"
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/*
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* As a rule of thumb, GPIO pins used by coreboot should be initialized at
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* bootblock while GPIO pins used only by the OS should be initialized at
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* ramstage.
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*/
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static const struct soc_amd_gpio gpio_set_stage_ram[] = {
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/* I2S SDIN */
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PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
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/* I2S LRCLK */
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PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
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/* not Blink */
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PAD_GPI(GPIO_11, PULL_UP),
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/* APU_ALS_INT# */
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PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
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/* NFC IRQ */
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PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
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};
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void mainboard_program_gpios(void)
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{
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gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
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}
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