9aebc19182
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
77 lines
2.0 KiB
C
77 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <gpio.h>
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#include "gpio.h"
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/* GPIO pins used by coreboot should be initialized in bootblock */
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static const struct soc_amd_gpio gpio_set_stage_reset[] = {
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/* TPM CS */
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PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE),
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/* ESPI_CS_L */
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PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
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/* ESPI_SOC_CLK */
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PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE),
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/* ESPI_DATA0 */
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PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE),
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/* ESPI_DATA1 */
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PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE),
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/* ESPI_DATA2 */
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PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE),
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/* ESPI_DATA3 */
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PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE),
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/* ESPI_ALERT_L */
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PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
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/* TPM IRQ */
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PAD_SCI(GPIO_130, PULL_UP, EDGE_LOW),
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/* SPI_ROM_REQ */
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PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE),
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/* SPI_ROM_GNT */
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PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE),
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/* KBRST_L */
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PAD_NF(GPIO_21, KBRST_L, PULL_NONE),
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/* Deassert PCIe Reset lines */
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/* PCIE_RST0_L */
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PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
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/* PCIE_RST1_L */
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PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
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/* PC beep to codec */
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PAD_NF(GPIO_91, SPKR, PULL_NONE),
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/* Enable UART 2 */
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/* UART2_RXD */
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PAD_NF(GPIO_136, UART2_RXD, PULL_NONE),
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/* UART2_TXD */
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PAD_NF(GPIO_138, UART2_TXD, PULL_NONE),
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/* Enable UART 0 */
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/* UART0_RXD */
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PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
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/* UART0_TXD */
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PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
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/* FANOUT0 */
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PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
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/* I2C0 SCL */
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PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
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/* I2C0 SDA */
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PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
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/* I2C1 SCL */
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PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
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/* I2C1 SDA */
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PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
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/* I2C2_SCL */
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PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
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/* I2C2_SDA */
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PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
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/* I2C3_SCL */
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PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
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/* I2C3_SDA */
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PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
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};
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void mainboard_program_early_gpios(void)
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{
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gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
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}
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