9aebc19182
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <soc/southbridge.h>
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#include <amdblocks/lpc.h>
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#include <device/pci_ops.h>
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#include <gpio.h>
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#include <soc/pci_devs.h>
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#include <drivers/uart/uart8250reg.h>
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#include <arch/io.h>
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#include "../gpio.h"
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/* Enable IO access to port, then enable UART HW control pins */
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static void enable_serial(unsigned int base_port, unsigned int io_enable)
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{
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u8 reg;
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pci_or_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, io_enable);
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/*
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* Remove this section if HW handshake is not needed. This is needed
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* only for those who don't have a modified serial cable (connecting
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* DCD to DTR and DSR, plus connecting RTS to CTS). When you buy cables
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* on any store, they don't have these modification.
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*/
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reg = inb(base_port + UART8250_MCR);
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reg |= UART8250_MCR_DTR | UART8250_MCR_RTS;
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outb(reg, base_port + UART8250_MCR);
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}
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void bootblock_mainboard_early_init(void)
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{
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fch_clk_output_48Mhz(2);
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/*
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* UARTs enabled by default at reset, just need RTS, CTS
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* and access to the IO address.
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*/
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enable_serial(0x03f8, DECODE_ENABLE_SERIAL_PORT0);
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enable_serial(0x02f8, DECODE_ENABLE_SERIAL_PORT1);
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}
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void bootblock_mainboard_init(void)
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{
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size_t num_gpios;
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const struct soc_amd_gpio *gpios;
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gpios = early_gpio_table(&num_gpios);
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gpio_configure_pads(gpios, num_gpios);
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}
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