9b230ae295
This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to DRAM ID 0. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
48 lines
1.0 KiB
Plaintext
48 lines
1.0 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <variant/ec.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <soc/intel/common/acpi/platform.asl>
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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Scope (\_SB) {
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#if CONFIG(HAVE_WWAN_POWER_SEQUENCE)
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#include "wwan_power.asl"
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#endif
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Device (PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/alderlake/acpi/southbridge.asl>
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#include <soc/intel/alderlake/acpi/tcss.asl>
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}
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}
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/* Chipset specific sleep states */
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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/* ChromeOS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#if CONFIG(INCLUDE_NVIDIA_GPU_ASL)
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#include "acpi/gpu_top.asl"
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#endif
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}
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