9bd6015843
Implement method to access the SuperIO's harware monitor (HWM) IO space. Set the PSU fan using a new CMOS option psu_fan_lvl. Add the CMOS option to all board that use NPCD378. In case no CMOS is set use the default fan level 3. The HWM space can be written to at any time, but the SuperIO has to be notified that a write is ongoing. After clearing the write-lock bit all changes are applied at once. Tested on HP Compaq 8200 SFF. Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26050 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
150 lines
4.6 KiB
C
150 lines
4.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <option.h>
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#include <pc80/keyboard.h>
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#include <stdlib.h>
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#include <superio/conf_mode.h>
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#include "npcd378.h"
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uint8_t npcd378_hwm_read(const uint16_t iobase, const uint16_t reg)
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{
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outb((reg >> 8) & 0xf, iobase + 0xff);
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uint8_t reg8 = inb(iobase + (reg & 0xff));
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if (reg8 == 0xff)
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reg8 = inb(iobase + (reg & 0xff));
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outb(0, iobase + 0xff);
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return reg8;
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}
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void npcd378_hwm_write(const uint16_t iobase, const uint16_t reg,
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const uint8_t val)
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{
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outb((reg >> 8) & 0xf, iobase + 0xff);
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outb(val, iobase + (reg & 0xff));
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outb(0, iobase + 0xff);
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}
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void npcd378_hwm_write_start(const uint16_t iobase)
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{
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u8 reg8 = npcd378_hwm_read(iobase, NPCD837_HWM_WRITE_LOCK_CTRL);
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reg8 &= ~NPCD837_HWM_WRITE_LOCK_BIT;
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npcd378_hwm_write(iobase, NPCD837_HWM_WRITE_LOCK_CTRL, reg8);
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}
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void npcd378_hwm_write_finished(const uint16_t iobase)
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{
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u8 reg8 = npcd378_hwm_read(iobase, NPCD837_HWM_WRITE_LOCK_CTRL);
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reg8 |= NPCD837_HWM_WRITE_LOCK_BIT;
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npcd378_hwm_write(iobase, NPCD837_HWM_WRITE_LOCK_CTRL, reg8);
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}
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static void npcd378_init(struct device *dev)
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{
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struct resource *res;
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uint8_t pwm, fan_lvl;
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if (!dev->enabled)
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return;
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switch (dev->path.pnp.device) {
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/* TODO: Might potentially need code for FDC etc. */
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case NPCD378_KBC:
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pc_keyboard_init(PROBE_AUX_DEVICE);
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break;
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case NPCD378_HWM:
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res = find_resource(dev, PNP_IDX_IO0);
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if (!res || !res->base) {
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printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n",
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NPCD378_HWM);
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break;
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}
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npcd378_hwm_write_start(res->base);
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if (!get_option(&fan_lvl, "psu_fan_lvl") || fan_lvl > 7)
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fan_lvl = 3;
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pwm = NPCD378_HWM_PSU_FAN_MIN +
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(NPCD378_HWM_PSU_FAN_MAX - NPCD378_HWM_PSU_FAN_MIN) *
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fan_lvl / 7;
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/* Set PSU fan PWM lvl */
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npcd378_hwm_write(res->base, NPCD378_HWM_PSU_FAN_PWM_CTRL, pwm);
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printk(BIOS_INFO, "NPCD378: PSU fan PWM 0x%02x\n", pwm);
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npcd378_hwm_write_finished(res->base);
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break;
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}
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = npcd378_init,
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.ops_pnp_mode = &pnp_conf_mode_8787_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ &ops, NPCD378_FDC, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, },
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{ &ops, NPCD378_PP, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, },
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{ &ops, NPCD378_SP1, PNP_IO0|PNP_IRQ0, 0x0ff8, },
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{ &ops, NPCD378_SP2, PNP_IO0|PNP_IRQ0, 0x0ff8, },
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{ &ops, NPCD378_PWR, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0|
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PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|
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PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE,
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0x0ff8, 0x0ff8},
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{ &ops, NPCD378_AUX, PNP_IRQ0, 0x0fff, 0x0fff, },
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{ &ops, NPCD378_KBC, PNP_IO0|PNP_IO1|PNP_IRQ0,
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0x0fff, 0x0fff, },
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{ &ops, NPCD378_WDT1, PNP_IO0|PNP_MSC8|PNP_MSC9|
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PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, 0x0ff8},
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{ &ops, NPCD378_HWM, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
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PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_IRQ0, 0x0ff8},
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{ &ops, NPCD378_GPIO_PP_OD, PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
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PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_MSC8|PNP_MSC9|PNP_MSCA|
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PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE},
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{ &ops, NPCD378_I2C, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0|
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PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|
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PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE,
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0x0ff8, 0x0ff8},
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{ &ops, NPCD378_SUSPEND, PNP_IO0, 0x0ff8 },
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{ &ops, NPCD378_GPIOA, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
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PNP_MSC4, 0x0ff8},
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_nuvoton_npcd378_ops = {
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CHIP_NAME("NUVOTON NPCD378 Super I/O")
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.enable_dev = enable_dev,
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};
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